CM0def.fth (4485B)
1 \ CortexDef.fth - default defininitions for Cortex CPUs 2 3 (( 4 Copyright (c) 2009 5 MicroProcessor Engineering 6 133 Hill Lane 7 Southampton SO15 5AF 8 England 9 10 tel: +44 (0)23 8063 1441 11 fax: +44 (0)23 8033 9691 12 net: mpe@mpeforth.com 13 tech-support@mpeforth.com 14 web: www.mpeforth.com 15 16 From North America, our telephone and fax numbers are: 17 011 44 23 8063 1441 18 011 44 23 8033 9691 19 20 21 Absolute addresses start with an '_' underscore character. 22 Offsets and masks do not. 23 24 25 To do 26 ===== 27 28 Change history 29 ============== 30 )) 31 32 33 \ *************** 34 \ Version numbers 35 \ *************** 36 37 char 7 equ mpe-rel \ x in Vx.yz 38 char 1 equ mpe-ver \ y in Vx.yz 39 char 0 equ usrver \ z in Vx.yz 40 41 \ *********** 42 \ Bit equates 43 \ *********** 44 45 $00000001 equ BIT0 46 $00000002 equ BIT1 47 $00000004 equ BIT2 48 $00000008 equ BIT3 49 $00000010 equ BIT4 50 $00000020 equ BIT5 51 $00000040 equ BIT6 52 $00000080 equ BIT7 53 $00000100 equ BIT8 54 $00000200 equ BIT9 55 $00000400 equ BIT10 56 $00000800 equ BIT11 57 $00001000 equ BIT12 58 $00002000 equ BIT13 59 $00004000 equ BIT14 60 $00008000 equ BIT15 61 $00010000 equ BIT16 62 $00020000 equ BIT17 63 $00040000 equ BIT18 64 $00080000 equ BIT19 65 $00100000 equ BIT20 66 $00200000 equ BIT21 67 $00400000 equ BIT22 68 $00800000 equ BIT23 69 $01000000 equ BIT24 70 $02000000 equ BIT25 71 $04000000 equ BIT26 72 $08000000 equ BIT27 73 $10000000 equ BIT28 74 $20000000 equ BIT29 75 $40000000 equ BIT30 76 $80000000 equ BIT31 77 78 79 \ ******* 80 \ Cortex-M0 CPU 81 \ ******* 82 83 \ ======================= 84 \ CPSR and mode switching 85 \ ======================= 86 87 \ CPSR/SPSR definitions _F _S _X _C 88 \ _F Flag bits (31..24) 89 bit31 equ N_bit \ negative 90 bit30 equ Z_bit \ zero 91 bit29 equ C_bit \ carry 92 bit28 equ V_bit \ overflow 93 bit27 equ Q_bit \ sticky overflow (saturation) 94 95 bit24 equ T_bit \ Jazelle 96 97 98 \ *************************************** 99 \ Interrupt handler equates for IntCortex.fth 100 \ *************************************** 101 102 0 equ StackVec# \ holds initial stack pointer 103 1 equ ResetVec# \ reset 104 2 equ NMIVec# \ NMI 105 3 equ HardVec# \ hard fault 106 4 equ MemVec# \ memory fault 107 5 equ BusVec# \ bus fault 108 6 equ UseVec# \ usage fault 109 110 #11 equ SvcVec# \ SVC/SWI 111 #12 equ DbgVec# \ Debug, e.g. breakpoint 112 113 #14 equ PendVec# \ Pendable request 114 #15 equ SysTickVec# \ System Ticker 115 116 \ Vectors 16..255 are implementation defined 117 118 119 \ ****************************** 120 \ Standard Cortex-M0 peripherals 121 \ ****************************** 122 123 $E000:E000 equ _SCS \ -- addr 124 \ Base of System Control Space 125 126 $0004 equ scsICTR \ Interrupt Controller Type Register - r/o 127 128 $0010 equ stCSR \ systick Control and Status Register 129 $0014 equ stRVR \ Reload Value Register 130 $0018 equ stCVR \ Current Value Register 131 $001C equ stCalib \ Calibration value register 132 133 $0100 equ nvSetEnR0 \ nvic Set Enable Reg 0..7 134 $0180 equ nvClrEnR0 \ Clear Enable reg 0..7 135 $0200 equ nvSetPendR0 \ Set Pending Reg 0..7 136 $0280 equ nvClrPendR0 \ Clr Pending Reg 0..7 137 \ $0300 equ nvABR0 \ Active Bit Reg 0..7 138 $0400 equ nvPR0 \ Priority Reg 0.. 139 140 $0D00 equ scsCPUID \ sys CPUID Base Register 141 $0D04 equ scsICSR \ Interrupt Control State Reg 142 \ $0D08 equ scsVTOR \ Vector table Offset Reg 143 $0D0C equ scsAIRCR \ Application Interrupt/Reset Control Reg 144 $0D10 equ scsSCR \ System Control Reg 145 $0D14 equ scsCCR \ Configuration Control reg 146 \ $0D18 equ scsSHPRB0 \ System Handler Priority Reg 2 147 $0D1C equ scsSHPR2 \ System Handler Priority Reg 2 148 $0D20 equ scsSHPR3 \ System Handler Priority Reg 2 149 150 151 \ ******************************************* 152 \ SYSm constants for MSR and MRS instructions 153 \ ******************************************* 154 155 decimal 156 157 0 equ APSR \ just the flags 158 5 equ IPSR \ just the exception number 159 6 equ EPSR \ just the execution state 160 161 1 equ IAPSR \ flags + exception 162 2 equ EAPSR \ flags + execution state 163 3 equ XPSR \ flags + execution + exception 164 7 equ IEPSR \ exception + execution 165 166 8 equ SP_main \ Main stack pointer (exceptions) 167 9 equ SP_process \ Process stack pointer (threads) 168 169 16 equ PRIMASK \ bit0=1 to enable NMI and HardFault 170 17 equ BASEPRI \ 9 bit priority (lower=higher priority) 171 18 equ BASEPRI_MAX 172 19 equ FAULTMASK \ bit0=1 to enable NMI only 173 20 equ CONTROL \ bit1=1 for SP_process, bit0=1 for User state in thread mode 174 \ we have bit0=0 always 175