liteSTM32F072sa.ctl (12759B)
1 \ liteSTM32F072sa.ctl - STM32F072RB discovery board standalone "Lite" Forth 2 3 (( 4 Copyright (c) 2014 5 MicroProcessor Engineering 6 133 Hill Lane 7 Southampton SO15 5AF 8 England 9 10 tel: +44 (0)23 8063 1441 11 fax: +44 (0)23 8033 9691 12 net: mpe@mpeforth.com 13 tech-support@mpeforth.com 14 web: www.mpeforth.com 15 16 From North America, our telephone and fax numbers are: 17 011 44 23 8063 1441 18 011 44 23 8033 9691 19 20 21 To do 22 ===== 23 24 Change history 25 ============== 26 20140707 MPE002 Updated for Lite Forth v2. 27 20140205 MPE001 First release for STM32F0xx. 28 )) 29 30 31 \ ================ 32 \ *! stm32f072litesa 33 \ *T Control file for STM32F072 Discovery board 34 \ ================ 35 \ *P Every Forth project has a control file, which is similar to the 36 \ ** project file in other languages. The control file tells the 37 \ ** cross compiler all about the target. Not all of it is 38 \ ** documented here, but it is all commented in the source code. 39 40 \ *P The control file *\i{CortexLite/Hardware/STM32F072Bdisco/liteSTM32F072sa.ctl} 41 \ ** produces a standalone Forth for the STM32F072B Discovery board. 42 \ ** The control files for other boards are very similar in structure, 43 \ ** and different in the details of the CPU and board specific 44 \ ** options. Read the specific code for your CPU and board. 45 46 \ *P The serial port is connected to USART1 on pins PA9 (Tx -> PC Rx) and 47 \ ** PA10 (Rx -> PC Tx). 48 \ ** You cannot use the easy GPIO code for UART initialisation unless 49 \ ** the GPIO ports are clocked and taken out of reset in the start 50 \ ** up code. 51 52 \ *P When you modify this file for your own hardware do not forget 53 \ ** to update the GPIO pin assignments and alternate function 54 \ ** selections. 55 56 \ *P To Flash the board, you can use the low-cost ST-LINK/V2 JTAG unit, or use 57 \ ** the one integrated into the ST Discovery boards. 58 \ ** The ST-LINK Utility software is a 59 \ ** free download from the ST website *\f{www.st.com}. 60 61 only forth definitions decimal 62 63 64 \ ************************** 65 \ *S Define directory macros 66 \ ************************** 67 \ *P The MPE cross compilers contain a useful text macro system. 68 \ ** Macros allow easy porting of control files when projects are 69 \ ** moved from their default locations. Each directory macro 70 \ ** defines where a particular set of files are located. 71 72 \ *[ 73 c" ." setmacro AppDir \ application files 74 c" ." setmacro HwDir \ Board hardware files 75 c" ..\.." setmacro CpuDir \ CPU specific files 76 c" ..\..\Examples" setmacro ExampleDir \ example files 77 \ *] 78 79 80 \ ***************************** 81 \ *S Turn on the cross compiler 82 \ ***************************** 83 84 \ *[ 85 86 include %CpuDir%/Macros \ macros needed by the cross-compiler 87 88 CROSS-COMPILE \ Turn host Forth into a cross-compiler 89 90 only forth definitions \ default search order 91 92 no-log \ uncomment to suppress output log 93 rommed \ split ROM/RAM target 94 interactive \ enter interactive mode at end 95 +xrefs \ enable cross references 96 align-long \ code is 32bit aligned 97 Cortex-M0 \ Thumb2 processor type and register usage 98 -LongCalls \ no calls outside 25 bit range 99 +FlashCompile \ target compiles to Flash 100 Hex-I32 \ also produce Intel Hex-32 obj format 101 +SaveCdataOnly \ no data area image files 102 103 0 equ false 104 -1 equ true 105 106 \ *] 107 108 \ ******************* 109 \ *S Configure target 110 \ ******************* 111 112 \ ============================== 113 \ *N STM32F0 variant definitions 114 \ ============================== 115 116 $0800:0000 equ FlashBase \ -- addr 117 \ *G Start address of Flash. The bottom 2kb (the vector area) is 118 \ ** mirrored at $0000:0000 for booting. 119 120 #128 kb equ /Flash \ -- len 121 \ *G Size of Flash. 122 2 kb equ /FlashPage \ -- len 123 \ *G Size of a Flash Page. 124 1 equ KeepPages \ -- u 125 \ *G Set this non-zero for the number of pages at the end of Flash 126 \ ** that are reserved for configuration data. Often set to 1 or 2 127 \ ** by systems that use PowerNet. 128 FlashBase /Flash + /FlashPage KeepPages * - equ CfgFlash \ -- len 129 \ *G Base address of the configuration Flash area. 130 131 $1FFF:C800 equ /InfoBase \ -- addr 132 \ *G Base address of system memory information block. 133 134 #12 kb equ /SysMem \ -- len 135 \ *G Size of system memory block. 136 137 $1FFF:F800 equ OptionBytes \ -- addr 138 \ *G Base address of option bytes 139 #16 equ /OptionBytes \ -- len 140 \ *G Number of option bytes 141 142 #64 cells equ /ExcVecs \ -- len 143 \ *G Size of the exception/interrupt vector table. There are 144 \ ** 16 slots reserved by ARM. 145 146 \ *P The system clocks are generated from PLLs. 147 \ ** How to set them up is non-obvious and is mostly documented 148 \ ** by the ST demonstration code in the file *\i{system_stm32f0x2.c}. 149 \ ** If you are not going to use an existing setup, copy and rename 150 \ ** one of the existing *\i{startSTM32F0xx.fth} files. 151 152 8 MHz equ xtal-speed \ -- hz 153 \ *G Master oscillator crystal clock rate in HZ. This is the HSI 154 \ ** internal oscillator which has better than +/-1% accuracy and 155 \ ** is more accurate than the internal 48 MHz oscillator. 156 48 MHz equ system-speed \ -- hz 157 \ *G Requested CPU clock speed in HZ. Note that you must 158 \ ** calculate the PLL values. 159 160 1 equ AHBdiv \ -- u 161 \ *G Division ratio of the AHB clock from the system clock. 162 \ ** This may not be more than 48 MHz. 163 1 equ APBdiv \ -- u 164 \ *G Division ratio of the APB clock from the system clock. 165 \ ** This may not be more than 48 MHz. 166 167 system-speed AHBdiv / equ AHB-speed \ -- hz 168 \ *G AHB bus speed. 169 system-speed APBdiv / equ APB-speed \ -- hz 170 \ *G APB bus speed. 171 172 173 \ ============= 174 \ *N Memory map 175 \ ============= 176 \ *P If you are using the *\fo{Reflash} code in the *\i{ReProg} 177 \ ** folder, note that the Flash reprogramming code uses RAM 178 \ ** from $2000:0000..$2000:0FFF and its mirrors. Ensure that 179 \ ** your stacks are outside this region. 180 181 \ *P The Flash memory starts at $0800:0000. The bottom 2 kb (the 182 \ ** vector area) is mirrored at $0000:0000. The top 4 kb (two 183 \ ** pages) is used to save autostart and application linkage 184 \ ** information. 185 186 \ *[ 187 $0800:0000 $0800:BFFF cdata section liteSTM32F072sa \ code 188 $2000:0000 $2000:0FFF udata section PROGu \ 4k UDATA RAM 189 $2000:1000 $2000:3FFF idata section PROGd \ 12k IDATA RAM 190 191 interpreter 192 : prog liteSTM32F072sa ; \ synonym 193 target 194 195 PROG PROGd PROGu CDATA \ use Code for HERE , and so on 196 197 $0801:F000 equ INFOSTART \ kernel status is saved here. 198 $0801:F800 equ APPSTART \ application data is saved here. 199 $0801:FFFF equ INFOEND \ end of kernel/application status data. 200 $2000:0000 equ RAMSTART \ start of RAM 201 $2000:4000 equ RAMEND \ end of RAM 202 $0800:0000 equ FLASHSTART \ start of Main Flash 203 $0810:0000 equ FLASHEND \ end of possible main Flash 204 $0800:C000 equ APPFLASHSTART \ start of application flash 205 $0801:F000 equ APPFLASHEND \ end of application flash 206 APPFLASHEND APPFLASHSTART - equ /APPFLASH \ size of application flash 207 208 APPFLASHSTART TargetFlashStart \ sets HERE at kernel start up 209 210 \ *] 211 212 213 \ ============================ 214 \ *N Stack and user area sizes 215 \ ============================ 216 217 \ *[ 218 $0F0 equ UP-SIZE \ size of each task's user area 219 $0F0 equ SP-SIZE \ size of each task's data stack 220 $0100 equ RP-SIZE \ size of each task's return stack 221 up-size rp-size + sp-size + 222 equ task-size \ size of TASK data area 223 \ define the number of cells of guard space at the top of the data stack 224 #2 equ sp-guard \ can underflow the data stack by this amount 225 226 $0100 equ TIB-LEN \ terminal i/p buffer length 227 228 \ define nesting levels for interrupts and SWIs. 229 2 equ #IRQs \ number of IRQ stacks, 230 \ shared by all IRQs (1 min) 231 0 equ #SVCs \ number of SVC nestings permitted 232 \ 0 is ok if SVCs are unused 233 \ *] 234 235 236 \ ========================== 237 \ *N Serial and ticker rates 238 \ ========================== 239 240 1 equ useUSART1? \ -- n 241 \ *G Set non-zero to compile code for USART1, 242 \ ** device *\fo{Console1}. 243 #115200 equ console1-speed 244 \ *G *\fo{Console1} speed in BPS. 245 246 0 equ useUSART2? \ -- n 247 \ *G Set non-zero to compile code for USART2, 248 \ ** device *\fo{Console2}. 249 #115200 equ console2-speed 250 \ *G *\fo{Console2} speed in BPS. 251 252 0 equ useUSART3? \ -- n 253 \ *G Set non-zero to compile code for USART3, 254 \ ** device *\fo{Console3}. 255 115200 equ console3-speed 256 \ *G *\fo{Console3} speed in BPS. 257 258 0 equ useUSART4? \ -- n 259 \ *G Set non-zero to compile code for USART4, 260 \ ** device *\fo{Console4}. 261 115200 equ console4-speed 262 \ *G *\fo{Console4} speed in BPS. 263 264 1 equ console-port \ -- n ; Designate serial port for terminal (0..n). 265 \ *G Ports 1..4 are the on-chip UARTs. The internal USB device 266 \ ** is port 10, and bit-banged ports are defined from 20 onwards. 267 268 #1 equ tick-ms \ -- ms 269 \ *G Timebase tick in ms. 270 271 272 \ ===================== 273 \ *N Software selection 274 \ ===================== 275 \ *P With 128 kb of Flash we can select a comfortable set of 276 \ ** software and still have plenty of space for application 277 \ ** code. 278 279 \ *[ 280 0 equ Tiny? \ nz to make a minimal kernel. 281 1 equ ColdChain? \ nz to use cold chain mechanism 282 1 equ tasking? \ true if multitasker needed 283 6 cells equ tcb-size \ for internal consistency check 284 0 equ timebase? \ true for TIMEBASE code 285 0 equ softfp? \ true for software floating point 286 0 equ FullCase? \ true to include ?OF END-CASE NEXTCASE extensions 287 0 equ target-locals? \ true if target local variable sources needed 288 0 equ romforth? \ true for ROMForth handler 289 0 equ blocks? \ true if BLOCK needed 290 $0000 equ sizeofheap \ 0=no heap, nz=size of heap 291 1 equ heap-diags? \ true to include diagnostic code 292 0 equ paged? \ true if ROM or RAM is paged/banked 293 \ *] 294 295 296 \ ***************** 297 \ default constants 298 \ ***************** 299 300 cell equ cell \ size of a cell (16 bits) 301 0 equ false 302 -1 equ true 303 304 305 \ *************** 306 \ *S Kernel files 307 \ *************** 308 309 \ *[ 310 include %CpuDir%/CM0def \ Cortex generic equates and SFRs 311 include %CpuDir%/sfrSTM32F072 \ STM32F072 special function registers 312 include %CpuDir%/StackDef \ Reserve default task and stacks 313 PROGd sec-top 1+ equ UNUSED-TOP PROG \ top of memory for UNUSED 314 include %HwDir%/startSTM32F072 \ start up code 315 l: crcslot 316 0 , \ the kernel CRC 317 l: crcstart 318 include %CpuDir%/CodeM0lite \ low level kernel definitions 319 include %CpuDir%/Drivers/FlashSTM32 \ Flash programming code 320 include %CpuDir%/kernel72lite \ high level kernel definitions 321 include %CpuDir%/Drivers/rebootSTM32 \ reboot using watchdog 322 include %CpuDir%/IntCortex \ interrupt handlers for NVIC 323 include %CpuDir%/FaultCortex \ fault exception handlers for NVIC 324 \ *] 325 : selio-ser1 \ -- 326 \ *G Example to perform clock and pin selection for USART1 on PA9/10. 327 \ ** You cannot use the easy GPIO code for this unless the GPIO ports 328 \ ** are clocked and taken out of reset in the start up code. 329 \ Clocks and reset 330 _RCC 331 $0000 $0003 2 pick rccCFGR3 + setMask \ PCLK is UART clock 332 bit17 over rccAHBen + or! \ enable clock to GPIOA 333 bit17 over rccAHBrst + bic! \ take it out of reset 334 bit14 over rccAPB2en + or! \ enable clock to USART1 335 bit14 over rccAPB2rst + bic! \ take it out of reset 336 drop 337 \ Default on PA9/10 338 _GPIOA >r 339 $0028:0000 $003C:0000 r@ gpioMODER + setMask \ alternate function on 9/10 340 $0000:0110 $0000:0FF0 r> gpioAFRH + setMask \ AF1 for both 341 ; 342 \ *[ 343 include %CpuDir%/Drivers/serSTM32F0xxp \ polled serial driver 344 include %CpuDir%/Dump \ DUMP .S etc development tools 345 346 include %CpuDir%/Drivers/gpioSTM32F0xx \ easy pin access 347 include %CpuDir%/Drivers/SysTickDisco072 348 ' start-clock AtCold 349 350 tasking? [if] 351 include %CpuDir%/MultiCM0lite \ multitasker 352 [then] 353 354 \ *] 355 356 357 \ ************* 358 \ *S End of kernel 359 \ ************* 360 \ *P After the main kernel has been built, some version data is 361 \ ** laid down for use by the sign-on code. 362 363 \ *[ 364 365 buildfile liteSTM32F072sa.no 366 l: version$ 367 build$, 368 l: BuildDate$ 369 DateTime$, 370 371 internal 372 : .banner \ -- 373 cr ." ****************************" 374 ; 375 376 : .CPU \ -- ; display CPU type 377 .banner 378 cr ." MPE Forth Lite for STM32F072" 379 cr version$ $. space BuildDate$ $. 380 cr ." Copyright (C) 2014 MicroProcessor Engineering Ltd." 381 .banner 382 ; 383 external 384 \ *] 385 386 387 \ ******************* 388 \ *S Application code 389 \ ******************* 390 \ *P This code is not essential, but makes life very much easier. 391 392 \ *[ 393 include %HwDir%/ReProg/ReFlash \ ReFlash utility 394 include %CpuDir%/include \ include from AIDE 395 include %CpuDir%/Drivers/spiSTM32F0hard \ SPI2 driver 396 include %CpuDir%/Examples/l3gd20 \ L3GD20 MEMS driver 397 398 RAMEND constant RP-END \ end of available RAM 399 \ *] 400 401 402 \ *************** 403 \ *S Finishing up 404 \ *************** 405 \ *[ 406 407 libraries \ to resolve common forward references 408 include %CpuDir%/LibM0M1 409 include %CpuDir%/LIBRARY 410 end-libs 411 412 decimal 413 414 \ Add a kernel checksum 415 crcstart here crcslot crc32 checksum 416 /DefStart 128 > [if] 417 .( DEFSTART area too big ) abort 418 [then] 419 420 update-build \ update build number file 421 422 FINIS \ all done 423 424 \ *] 425 426 427 \ ====== 428 \ *> ### 429 \ ======