liteSTM32F072uf.ctl (13370B)
1 \ liteSTM32F072uf.ctl - Umbilical Forth STM32F072RB discovery board 2 3 (( 4 Copyright (c) 2014 5 MicroProcessor Engineering 6 133 Hill Lane 7 Southampton SO15 5AF 8 England 9 10 tel: +44 (0)23 8063 1441 11 fax: +44 (0)23 8033 9691 12 net: mpe@mpeforth.com 13 tech-support@mpeforth.com 14 web: www.mpeforth.com 15 16 From North America, our telephone and fax numbers are: 17 011 44 23 8063 1441 18 011 44 23 8033 9691 19 20 21 To do 22 ===== 23 24 Change history 25 ============== 26 20140409 MPE001 First release for STM32F0xx. 27 )) 28 29 30 \ ================ 31 \ *! stm32f072liteuf 32 \ *T Umbilical Forth for STM32F072 Discovery board 33 \ ================ 34 \ *P The control file *\i{Cortex/Hardware/STM32F0/liteSTM32F072uf.ctl} 35 \ ** produces an Umbilical Forth for the STM32F072 Discovery board. 36 \ ** The serial port is connected to USART1 on pins PA9 (Tx) and 37 \ ** PA10 (Rx). 38 \ ** You cannot use the easy GPIO code for UART initialisation unless 39 \ ** the GPIO ports are clocked and taken out of reset in the start 40 \ ** up code. 41 42 \ *P When you modify this file for your own hardware do not forget 43 \ ** to update the GPIO pin assignments and alternate function 44 \ ** selections. 45 46 \ *P You can easily use the low-cost ST-LINK/V2 JTAG unit. 47 \ ** The ST-LINK Utility software is a 48 \ ** free download from the ST website *\f{www.st.com}. 49 50 only forth definitions decimal 51 52 53 \ ****************************** 54 \ Define the default directories 55 \ ****************************** 56 57 c" ." setmacro AppDir \ application files 58 c" ." setmacro HwDir \ Board hardware files 59 c" ." setmacro CpuDir \ CPU specific files 60 c" ..\Examples" setmacro ExampleDir \ example files 61 62 63 \ *************************************** 64 \ Load compiler extensions such as macros 65 \ *************************************** 66 67 include %CpuDir%/Macros 68 69 70 \ ********************************************************* 71 \ Turn on the cross compiler and define CPU and log options 72 \ ********************************************************* 73 74 \ file: PROG.log \ uncomment to send log to a file 75 76 CROSS-COMPILE 77 78 Only Forth Definitions \ default search order 79 80 no-heads \ No heads on target 81 No-log \ No output log 82 Rommed \ Split ROM/RAM system 83 +xrefs \ enable cross references 84 align-long \ code is 32bit aligned 85 Cortex-M0 \ Thumb2 processor type and register usage 86 -LongCalls \ no calls outside 25 bit range 87 Hex-I32 \ also produce Intel Hex-32 obj format 88 +SaveCdataOnly \ no data area image files 89 90 0 equ false 91 -1 equ true 92 93 94 \ ******************* 95 \ *S Configure target 96 \ ******************* 97 98 \ ====================== 99 \ *N STM32F0 variant definitions 100 \ ====================== 101 102 $0800:0000 equ FlashBase \ -- addr 103 \ *G Start address of Flash. The bottom 2kb (the vector area) is 104 \ ** mirrored at $0000:0000 for booting. 105 106 #128 kb equ /Flash \ -- len 107 \ *G Size of Flash. 108 2 kb equ /FlashPage \ -- len 109 \ *G Size of a Flash Page. 110 1 equ KeepPages \ -- u 111 \ *G Set this non-zero for the number of pages at the end of Flash 112 \ ** that are reserved for configuration data. Often set to 1 or 2 113 \ ** by systems that use PowerNet. 114 FlashBase /Flash + /FlashPage KeepPages * - equ CfgFlash \ -- len 115 \ *G Base address of the configuration Flash area. 116 117 $1FFF:C800 equ /InfoBase \ -- addr 118 \ *G Base address of system memory information block. 119 120 #12 kb equ /SysMem \ -- len 121 \ *G Size of system memory block. 122 123 $1FFF:F800 equ OptionBytes \ -- addr 124 \ *G Base address of option bytes 125 #16 equ /OptionBytes \ -- len 126 \ *G Number of option bytes 127 128 #64 cells equ /ExcVecs \ -- len 129 \ *G Size of the exception/interrupt vector table. There are 130 \ ** 16 reserved by ARM. 131 132 \ *P The system clocks are generated from PLLs. 133 \ ** How to set them up is non-obvious and is mostly documented 134 \ ** by the ST demonstration code in the file *\i{system_stm32f0x2.c}. 135 \ ** If you are not going to use an existing setup, copy and rename 136 \ ** one of the existing *\i{startSTM32F0xx.fth} files. 137 138 8 MHz equ xtal-speed \ -- hz 139 \ *G Master oscillator crystal clock rate in HZ. This is the HSI 140 \ ** internal oscillator which has better than +/-1% accuracy and 141 \ ** is more accurate than the internal 48 MHz oscillator. 142 48 MHz equ system-speed \ -- hz 143 \ *G Requested CPU clock speed in HZ. Note that you must 144 \ ** calculate the PLL values. 145 146 1 equ AHBdiv \ -- u 147 \ *G Division ratio of the AHB clock from the system clock. 148 \ ** This may not be more than 48 MHz. 149 1 equ APBdiv \ -- u 150 \ *G Division ratio of the APB clock from the system clock. 151 \ ** This may not be more than 48 MHz. 152 153 system-speed AHBdiv / equ AHB-speed \ -- hz 154 \ *G AHB bus speed. 155 system-speed APBdiv / equ APB-speed \ -- hz 156 \ *G APB bus speed. 157 158 159 \ ============= 160 \ *N Memory map 161 \ ============= 162 \ *P If you are using the *\fo{Reflash} code in the *\i{ReProg} 163 \ ** folder, note that the Flash reprogramming code uses RAM 164 \ ** from $2000:0000..$2000:0FFF and its mirrors. Ensure that 165 \ ** your stacks are outside this region. 166 167 \ *P The Flash memory starts at $0800:0000. The bottom 2 kb (the 168 \ ** vector area) is mirrored at $0000:0000. The top 4 kb (two 169 \ ** pages) is used to save autostart and application linkage 170 \ ** information. 171 172 $0800:0000 $0800:FFFF cdata section liteSTM32F072uf \ code section in boot Flash 173 $2000:0000 $2000:0FFF idata section PROGd \ 4k IDATA 174 $2000:1000 $2000:3FFF udata section PROGu \ 12k UDATA 175 176 interpreter 177 : prog liteSTM32F072uf ; \ synonym 178 target 179 180 PROG PROGd PROGu CDATA \ use Code for HERE , and so on 181 182 183 \ ============================ 184 \ *N Stack and user area sizes 185 \ ============================ 186 \ *P These equates calculate how much RAM is needed for the USER area, 187 \ ** Return stack and data stack of each task, plus an area used 188 \ ** by Forth interrupts that share a common USER (and optionally) 189 \ ** common stacks. This can be done to reduce the overall amount 190 \ ** of RAM needed for interrupt stacks. Since interrupts can occur 191 \ ** in any task, switching stacks for high level interrupts will 192 \ ** reduce the total RAM requirements. 193 194 $040 equ UP-SIZE \ size of each task's user area 195 $080 equ SP-SIZE \ size of each task's data stack 196 $080 equ RP-SIZE \ size of each task's return stack 197 up-size rp-size + sp-size + 198 equ task-size \ size of TASK data area 199 \ define the number of cells of guard space at the top of the data stack 200 #2 equ sp-guard \ can underflow the data stack by this amount 201 202 203 SP-SIZE 2 rshift 2 - equ max-depth \ max depth for UF data stack 204 205 \ define nesting levels for interrupts and SWIs. 206 2 equ #IRQs \ number of IRQ stacks, 207 \ shared by all IRQs (1 min) 208 0 equ #SVCs \ number of SVC nestings permitted 209 \ 0 is ok if SVCs are unused 210 211 212 \ ========================== 213 \ *N Serial and ticker rates 214 \ ========================== 215 216 1 equ useUSART1? \ -- n 217 \ *G Set non-zero to compile code for USART1, 218 \ ** device *\fo{Console1}. 219 #115200 equ console1-speed 220 \ *G *\fo{Console1} speed in BPS. 221 222 0 equ useUSART2? \ -- n 223 \ *G Set non-zero to compile code for USART2, 224 \ ** device *\fo{Console2}. 225 #115200 equ console2-speed 226 \ *G *\fo{Console2} speed in BPS. 227 228 0 equ useUSART3? \ -- n 229 \ *G Set non-zero to compile code for USART3, 230 \ ** device *\fo{Console3}. 231 115200 equ console3-speed 232 \ *G *\fo{Console3} speed in BPS. 233 234 0 equ useUSART4? \ -- n 235 \ *G Set non-zero to compile code for USART4, 236 \ ** device *\fo{Console4}. 237 115200 equ console4-speed 238 \ *G *\fo{Console4} speed in BPS. 239 240 1 equ console-port \ -- n ; Designate serial port for terminal (0..n). 241 \ *G Ports 1..4 are the on-chip UARTs. The internal USB device 242 \ ** is port 10, and bit-banged ports are defined from 20 onwards. 243 244 #1 equ tick-ms \ -- ms 245 \ *G Timebase tick in ms. 246 247 248 \ ===================== 249 \ *N Software selection 250 \ ===================== 251 252 1 equ umbilical? \ true = Umbilical Forth, zero = standalone 253 0 umbilical? and equ SPI? \ true for SPI Umbilical, false for serial 254 SPI? 0= equ Serial? \ true for Serial Umbilical, false for SPI 255 1 equ init-idata? \ true if IDATA to be initialised 256 257 \ Kernel components 258 0 equ ColdChain? \ nz to use cold chain mechanism 259 0 equ tasking? \ true if multitasker needed 260 6 cells equ tcb-size \ for internal consistency check 261 0 equ event-handler? \ true to include event handler 262 0 equ message-handler? \ true to include message handler 263 1 equ semaphores? \ true to include semaphores 264 0 equ timebase? \ true for TIMEBASE code 265 0 equ softfp? \ true for software floating point 266 0 equ FullCase? \ true to include ?OF END-CASE NEXTCASE extensions 267 0 equ target-locals? \ true if target local variable sources needed 268 0 equ romforth? \ true for ROMForth handler 269 0 equ blocks? \ true if BLOCK needed 270 $0000 equ sizeofheap \ 0=no heap, nz=size of heap 271 0 equ heap-diags? \ true to include diagnostic code 272 0 equ paged? \ true if ROM or RAM is paged/banked 273 0 equ MPE-SET? \ compatibility with MPE v5 targets 274 0 equ ENVIRONMENT? \ true if ANS ENVIRONMENT system required 275 276 interpreter 277 : AtCold \ xt -- 278 \ *G Most Umbilical Forth systems do not use the *\fo{ColdChain} 279 \ ** mechanism provided in *\i{Kernel62.fth} for standalone 280 \ ** Forths. To prevent compilation problems, define *\fo{AtCold} 281 \ ** as *\fo{DROP}. Compilers built from December 2008 onwards 282 \ ** will warn you if *\fo{AtCold} is used before being defined 283 \ ** in the target code. 284 drop 285 ; 286 target 287 288 289 \ ************ 290 \ *S Kernel files 291 \ ************ 292 293 include %CpuDir%/CM0def \ Cortex generic equates and SFRs 294 include %CpuDir%/sfrSTM32F072 \ STM32F072 special function registers 295 include %CpuDir%/StackDef \ Reserve default task and stacks 296 PROGd sec-top 1+ equ UNUSED-TOP PROG \ top of memory for UNUSED 297 include %HwDir%/startSTM32F072 \ start up code 298 include %CpuDir%/minM0M1 \ code definitions 299 : selio-ser1 \ -- 300 \ *G Example to perform clock and pin selection for USART1 on PA9/10. 301 \ ** You cannot use the easy GPIO code for this unless the GPIO ports 302 \ ** are clocked and taken out of reset in the start up code. 303 \ Clocks and reset 304 _RCC 305 $0000 $0003 2 pick rccCFGR3 + setMask \ PCLK is UART clock 306 bit17 over rccAHBen + or! \ enable clock to GPIOA 307 bit17 over rccAHBrst + bic! \ take it out of reset 308 bit14 over rccAPB2en + or! \ enable clock to USART1 309 bit14 over rccAPB2rst + bic! \ take it out of reset 310 drop 311 \ Default on PA9/10 312 _GPIOA >r 313 $0028:0000 $003C:0000 r@ gpioMODER + setMask \ alternate function on 9/10 314 $0000:0110 $0000:0FF0 r> gpioAFRH + setMask \ AF1 for both 315 ; 316 include %CpuDir%/Drivers/serSTM32F0xxp \ polled serial driver 317 Include %CpuDir%/UFKernel \ Umbilical Forth high level kernel 318 umbilical? [if] 319 Synonym wait-byte serkey1 \ Say which XTL drivers to use 320 Synonym send-byte seremit1 321 Synonym Wait-Byte? serkey?1 322 Synonym Init-XTL Init-Ser 323 include %CpuDir%/MESSAGES \ Umbilical message equates 324 include %CpuDir%/Targend \ message driver 325 [then] 326 327 328 \ ************* 329 \ *S End of kernel 330 \ ************* 331 332 : .CPU \ -- ; sign on 333 ." MPE STM32F072 " 334 [ Umbilical? ] [if] ." Umbilical " [else] ." Production " [then] 335 ." Forth" 336 ; 337 338 339 \ ************************** 340 \ Load application code here 341 \ ************************** 342 343 \ include %AppDir%\MyApp \ you can use a macro for APPDIR 344 345 346 \ ******************* 347 \ Load libraries here 348 \ ******************* 349 350 libraries 351 include %CpuDir%/libM0M1 352 include %CPuDir%/UFlib 353 end-libs 354 355 356 \ ************************************** 357 \ Define what happens at target power up 358 \ ************************************** 359 360 (( 361 : test-UART \ -- char 362 ipvec @ >r opvec @ >r \ currently points to VUART 363 init-ser \ initialise UART 364 console0 dup ipvec ! opvec ! \ switch o/p to UART 365 ." Is the UART working? " key 366 r> opvec ! r> ipvec ! 367 ; 368 )) 369 370 Umbilical? [if] 371 make-turnkey run-umbilical \ in TARGEND.FTH 372 373 \ Segger J-Link - Windows, OS X, Linux 374 \ jlink STM32F072RB 1000 Project.jlink \ device, speed, project file 375 \ useSWD \ use SWD rather than the default JTAG 376 \ PSUART0 set-sjl-link \ select Umbilical link through J-Link 377 \ Windows - USB serial port 378 c" \\.\COM14" console1-speed serial \ define link driver 379 c" dtr=off rts=off" ser-control \ define DTR and RTS 380 \ OS X - Keyspan HS19 USB adapter 381 \ c" /dev/cu.KeySerial1" console0-speed serial \ define link driver 382 \ c" 1 dtr 1 rts" ser-control \ define DTR and RTS 383 384 cr ." You only need to download the LITESTM32F072UF section." 385 cr ." Program the Flash using the ST-Link utility" 386 cr ." Then answer N to the erase the Flash question." 387 cr 388 cr ." When you get the T:OK prompt, type .CPU to run" 389 cr ." the word .CPU from this file." 390 cr 391 \ cr ." Press any key to continue" key drop 392 \ cr 393 394 umbilical-forth \ start interactive session 395 [else] 396 : test-start \ -- 397 init-ser \ initialise the serial port for our use 398 console ipvec ! console opvec ! \ I/O goes to VUART 399 c" This is the STM32F072 Chip speaking!" 400 count 0 401 do dup c@ emit 1+ loop \ drop 402 begin 403 key emit 404 again 405 ; 406 407 Make-turnkey test-start \ application start up word 408 [then] 409 410 finis 411