sfrSTM32F072.fth (11950B)
1 \ sfrSTM32F072.fth - peripheral definitions for STM32F0x1/2/8 2 3 (( 4 Copyright (c) 2010, 2012, 2013, 2014 5 MicroProcessor Engineering 6 133 Hill Lane 7 Southampton SO15 5AF 8 England 9 10 tel: +44 (0)23 8063 1441 11 fax: +44 (0)23 8033 9691 12 email: mpe@mpeforth.com 13 tech-support@mpeforth.com 14 web: http://www.mpeforth.com 15 Skype: mpe_sfp 16 17 From North America, our telephone and fax numbers are: 18 011 44 23 8063 1441 19 011 44 23 8033 9691 20 901 313 4312 (North American access number to UK office) 21 22 23 To do 24 ===== 25 26 Change history 27 ============== 28 )) 29 30 only forth definitions 31 decimal 32 33 34 \ =========== 35 \ *! sfrstm32f072 36 \ *T STM32F072 memory and peripherals 37 \ =========== 38 39 40 \ ******************************** 41 \ Memory/Peripheral base addresses 42 \ ******************************** 43 44 $0800:0000 equ _FLASH \ up to 128 kb 45 46 $1FFF:C800 equ _SYSTEM \ 12 kb to 1FFF:F7FF 47 $1FFF:F800 equ _OPTION \ 2 kb to 1FFF:FFFF 48 49 $2000:0000 equ _SRAM \ 40 kb 50 $2200:0000 equ _SRAM_BB \ bit-band region 51 52 $4000:0000 equ _APB 53 $4000:0000 equ _APB1 54 $4001:0000 equ _APB2 55 $4200:0000 equ _PERIPH_BB \ bit-band region 56 57 $4800:0000 equ _AHB2 58 $4002:0000 equ _AHB1 59 60 61 \ *********************** 62 \ Flash memory controller 63 \ *********************** 64 65 \ Flash Program Erase Controller (FPEC) registers base address 66 $4002:2000 equ _FPEC \ _AHB1 0x3c00 + 67 68 \ Register offsets 69 $00 equ flACR 70 $04 equ flKEYR 71 $08 equ flOPTKEYR 72 $0C equ flSR 73 $10 equ flCR 74 $14 equ flAR 75 76 $1C equ flOBR 77 $20 equ flWRPR 78 79 $00A5 equ flRDPRTkey \ keys needed to write registers 80 $45670123 equ flKEY1 81 $CDEF89AB equ flKEY2 82 83 84 \ *** 85 \ CRC 86 \ *** 87 88 $4002:3000 equ _CRC \ AHB1 89 $00 equ crcDR 90 $04 equ crcIDR 91 $08 equ crcCR 92 93 $10 equ crcINIT 94 $14 equ crcPOL 95 96 97 \ ******************* 98 \ PWR - Power Control 99 \ ******************* 100 101 $4000:7000 equ _PWR \ _APB1 0x7000 + 102 $00 equ pwrCR 103 $04 equ pwrCSR 104 105 106 \ *********************** 107 \ Reset and Clock Control 108 \ *********************** 109 110 $4002:1000 equ _RCC \ AHB1 111 112 \ Register offsets 113 $00 equ rccCR \ Control Reg 114 $04 equ rccCFGR \ Clock Configuration 115 $08 equ rccCIR \ Clock Interrupt 116 $0C equ rccAPB2rst \ ABP2 reset 117 $10 equ rccAPB1rst \ APB1 reset 118 $14 equ rccAHBen \ AHB clock enable 119 $18 equ rccAPB2en \ APB2 clock enable 120 $1C equ rccAPB1en \ APB1 clock enable 121 $20 equ rccBDCR \ Backup Domain Control Reg 122 $24 equ rccCSR \ Control and Status Reg 123 $28 equ rccAHBrst \ AHB reset Reg, bit14=Ether, bit12=USB_OTG 124 $2C equ rccCFGR2 \ Clock Config Reg 2 125 $30 equ rccCFGR3 \ Clock Config Reg 3 126 $34 equ rccCR2 \ Control Reg 2 127 128 129 \ *************************** 130 \ CRS - Clock Recovery System 131 \ *************************** 132 133 $4000:6C00 equ _CRS \ APB 134 $00 equ crsCR 135 $04 equ crsCFGR 136 $08 equ crsISR 137 $0C equ crsICR 138 139 140 \ *********** 141 \ GPIO Blocks 142 \ *********** 143 144 $4800:0000 equ _GPIOA \ AHB2 145 $4800:0400 equ _GPIOB 146 $4800:0800 equ _GPIOC 147 $4800:0C00 equ _GPIOD 148 $4800:1000 equ _GPIOE 149 $4800:1400 equ _GPIOF 150 151 152 \ Register offsets 153 $00 equ gpioMODER \ mode register 154 $04 equ gpioOTYPER \ output type 155 $08 equ gpioOSPEEDR \ output speed 156 $0C equ gpioPUPDR \ pull up / pull down 157 $10 equ gpioIDR \ input data reg 158 $14 equ gpioODR \ output data reg 159 $18 equ gpioBSRR \ bit set / reset as 32 bit register 160 $18 equ gpioBSRRL \ low 16 bits to set 161 $1A equ gpioBSRRH \ high 16 bits to clear 162 $1C equ gpioLCKR \ configuration lock 163 $20 equ gpioAFRL \ alternate function low (4 bits per I/O pin) 164 $24 equ gpioAFRH \ alternate function high (4 bits per I/O pin) 165 $28 equ gpioBRR \ port bit reset 166 167 168 \ ******************************* 169 \ System Configuration Controller 170 \ ******************************* 171 172 $4001:0000 equ _SYSCFG \ APB2 173 $4001:0000 equ _COMP \ APB2 174 $4001:0000 equ _OPAMP \ APB2 175 $00 equ sysCFGR1 \ memory remap register, offset: 0x00 176 177 $08 equ sysEXTICR1 \ external interrupt configuration reg, offset: 0x08-0x14 178 $0C equ sysEXTICR2 179 $10 equ sysEXTICR3 180 $14 equ sysEXTICR4 181 $18 equ sysCFGR2 \ config reg 2 182 183 $1C equ compCSR 184 $1C equ comp1CSR 185 186 187 \ **************************** 188 \ External Event and Interrupt - EXTI 189 \ **************************** 190 191 $4001:0400 equ _EXTI 192 $00 equ extiIMR 193 $04 equ extiEMR 194 $08 equ extiRTSR 195 $0C equ extiFTSR 196 $10 equ extiSWIER 197 $14 equ extiPR 198 199 $00 equ extiIMR1 200 $04 equ extiEMR1 201 $08 equ extiRTSR1 202 $0C equ extiFTSR1 203 $10 equ extiSWIER1 204 $14 equ extiPR1 205 206 207 \ *** 208 \ DMA 209 \ *** 210 211 $4002:0000 equ _DMA \ AHB1 212 $4002:0000 equ _DMA1 \ AHB1 213 $000 equ dmaISR \ interrupt status 214 $004 equ dmaIFCR \ interrupt flag clear (write 1) 215 \ channel 1 - 20 bytes per DMA channel 216 $008 equ dmaCCR1 217 $00C equ dmaCNDTR1 218 $010 equ dmaCPAR1 219 $014 equ dmaCMAR1 220 \ channel 2 221 $01C equ dmaCCR2 222 $020 equ dmaCNDTR2 223 $024 equ dmaCPAR2 224 $028 equ dmaCMAR2 225 \ channel 3 226 $030 equ dmaCCR3 227 $034 equ dmaCNDTR3 228 $038 equ dmaCPAR3 229 $03C equ dmaCMAR3 230 \ channel 4 231 $044 equ dmaCCR4 232 $048 equ dmaCNDTR4 233 $04C equ dmaCPAR4 234 $050 equ dmaCMAR4 235 \ channel 5 236 $058 equ dmaCCR5 237 $05C equ dmaCNDTR5 238 $060 equ dmaCPAR5 239 $064 equ dmaCMAR5 240 \ channel 6 - 07x only 241 $06C equ dmaCCR6 242 $070 equ dmaCNDTR6 243 $074 equ dmaCPAR6 244 $078 equ dmaCMAR6 245 \ channel 7 -07x only 246 $080 equ dmaCCR7 247 $084 equ dmaCNDTR7 248 $088 equ dmaCPAR7 249 $08C equ dmaCMAR7 250 251 252 \ ****************************** 253 \ Ananlogue to Digital Converter - ADC 254 \ ****************************** 255 256 $4001:2400 equ _ADC \ APB 257 258 $00 equ adcISR 259 $04 equ adcIER 260 $08 equ adcCR 261 $0C equ adcCFGR1 262 $10 equ adcCFGR2 263 $14 equ adcSMPR1 264 265 $20 equ adcTR 266 267 $28 equ adcCHSELR 268 269 $40 equ adcDR 270 271 $308 equ adcCCR 272 273 274 \ ***************************** 275 \ Digital to Analogue Converter - DAC 276 \ ***************************** 277 278 $4000:7400 equ _DAC 279 $00 equ dacCR 280 $04 equ dacSWTRIGR 281 $08 equ dacDHR12R1 282 $0C equ dacDHR12L1 283 $10 equ dacDHR8R1 284 $14 equ dacDHR12R2 285 $18 equ dacDHR12L2 286 $1C equ dacDHR8R2 287 $20 equ dacDHR12RD 288 $24 equ dacDHR12LD 289 $28 equ dacDHR8RD 290 $2C equ dacDOR1 291 $30 equ dacDOR2 292 $34 equ dacSR 293 294 295 \ ****** 296 \ Timers 297 \ ****** 298 \ Not all timers have all registers 299 300 $4001:2C00 equ _TIM1 \ APB2 301 $4000:0000 equ _TIM2 \ APB1 302 $4000:0400 equ _TIM3 \ APB1 303 \ $4000:0800 equ _TIM4 \ APB1 304 305 $4000:1000 equ _TIM6 \ APB1 306 $4000:1400 equ _TIM7 \ APB1 307 \ $4001:3400 equ _TIM8 \ APB2 308 309 $4000:2000 equ _TIM14 \ APB 310 $4001:4000 equ _TIM15 \ APB2 311 $4001:4400 equ _TIM16 \ APB2 312 $4001:4800 equ _TIM17 \ APB2 313 $00 equ timCR1 314 $04 equ timCR2 315 $08 equ timSMCR 316 $0C equ timDIER 317 $10 equ timSR 318 $14 equ timEGR 319 $18 equ timCCMR1 320 $1C equ timCCMR2 321 $20 equ timCCER 322 $24 equ timCNT 323 $28 equ timPSC 324 $2C equ timARR 325 $30 equ timRCR 326 $34 equ timCCR1 327 $38 equ timCCR2 328 $3C equ timCCR3 329 $40 equ timCCR4 330 $44 equ timBDTR 331 $48 equ timDCR 332 $4C equ timDMAR 333 334 $50 equ timOR 335 $54 equ timCCMR3 336 \ $58 equ timCCR5 337 \ $5C equ timCCR6 338 339 340 \ **************** 341 \ IRTIM - Infrared 342 \ **************** 343 \ No specific registers, use TIM16/17 344 345 346 \ ******************** 347 \ Independent Watchdog 348 \ ******************** 349 350 $4000:3000 equ _IWDG \ _APB1 351 352 $00 equ iwdgKR 353 $04 equ iwdgPR 354 $08 equ iwdgRLR 355 $0C equ iwdgSR 356 $10 equ iwdgWINR 357 358 359 \ ***************** 360 \ Windowed Watchdog 361 \ ***************** 362 363 $4000:2C00 equ _WWDG \ _APB1 364 $00 equ wwdgCR 365 $04 equ wwdgCFR 366 $08 equ wwdgSR 367 368 369 \ === 370 \ RTC 371 \ === 372 373 $4000:2800 equ _RTC \ APB1 374 $000 equ rtcTR \ time 375 $004 equ rtcDR \ date 376 $008 equ rtcCR \ control 377 $00C equ rtcISR \ initialisation 378 $010 equ rtcPRER \ prescaler 379 $014 equ rtcWUTR \ wakeup timer 380 381 $01C equ rtcALRMAR \ alarm A 382 \ $020 equ rtcALRMBR \ alarm B 383 $024 equ rtcWPR \ write protect 384 $028 equ rtcSSR \ subsecond 385 $02C equ rtcSHIFTR \ shift control 386 $030 equ rtcTSTR \ timestamp time 387 $034 equ rtcTSDR \ timestamp date 388 $038 equ rtcTSSSR \ timestamp subsecond 389 $03C equ rtcCALR \ calibration 390 $040 equ rtcTAFCR \ tamper, alt func cfg 391 $044 equ rtcALRMASSR \ alarm A subsecond 392 \ $048 equ rtcALRMBSSR \ alarm B subsecond 393 394 $050 equ rtcBKP0R \ backup BBRMA $50..60 (20 bytes) 395 396 397 \ *** 398 \ I2C 399 \ *** 400 401 $4000:5400 equ _I2C1 \ APB1 402 $4000:5800 equ _I2C2 \ APB1 403 $00 equ i2cCR1 404 $04 equ i2cCR2 405 $08 equ i2cOAR1 406 $0C equ i2cOAR2 407 $10 equ i2cTIMINGR 408 $14 equ i2cTIMEOUTR 409 $18 equ i2cISR 410 $1C equ i2cICR 411 $20 equ i2cPECR 412 $24 equ i2cRXDR 413 $28 equ i2cTXDR 414 415 416 \ ************ 417 \ USART blocks 418 \ ************ 419 420 $4001:3800 equ _USART1 \ APB2 421 $4000:4400 equ _USART2 \ APB1 422 $4000:4800 equ _USART3 \ APB1 423 $4000:4C00 equ _USART4 \ APB1 424 \ $4000:5000 equ _UART5 \ APB1 425 $00 equ usCR1 426 $04 equ usCR2 427 $08 equ usCR3 428 $0C equ usBRR 429 $10 equ usGTPR 430 $14 equ usRTOR 431 $18 equ usRQR 432 $1C equ usISR 433 $20 equ usICR 434 $24 equ usRDR 435 $28 equ usTDR 436 437 438 \ ********** 439 \ SPI blocks 440 \ ********** 441 442 $4001:3000 equ _SPI1 \ APB2 443 $4000:3800 equ _SPI2 \ APB1 444 \ $4000:3C00 equ _SPI3 \ APB1 445 $000 equ spiCR1 446 $004 equ spiCR2 447 $008 equ spiSR 448 $00C equ spiDR 449 $010 equ spiCRCPR 450 $014 equ spiRXCRCR 451 $018 equ spiTXCRCR 452 $01C equ spiI2SCFGR 453 $020 equ spiI2SPR 454 455 456 \ ************************ 457 \ Touch Sensing Controller - TSC 458 \ ************************ 459 460 $4002:4000 equ _TSC \ AHB1 461 $00 equ tscCR 462 $04 equ tscIER 463 $08 equ tscICR 464 $0C equ tscISR 465 $10 equ tscIOHCR 466 467 $18 equ tscIOASCR 468 469 $20 equ tscIOSCR 470 471 $28 equ tscIOCCR 472 473 $30 equ tscIOGCSR 474 $34 equ tscIOG1CR 475 $38 equ tscIOG2CR 476 $3C equ tscIOG3CR 477 $40 equ tscIOG4CR 478 $44 equ tscIOG5CR 479 $48 equ tscIOG6CR 480 $4C equ tscIOG7CR 481 $50 equ tscIOG8CR 482 483 484 \ ***** 485 \ bxCAN 486 \ ***** 487 488 $4000:6400 equ _bxCAN 489 $00 equ canMCR 490 $04 equ canMSR 491 $08 equ canTSR 492 $0C equ canRF0R 493 $10 equ canRF1R 494 $14 equ canIER 495 $18 equ canESR 496 $1C equ canBTR 497 498 $180 equ canTI0R 499 $184 equ canTDT0R 500 $188 equ canTDL0R 501 $18C equ canTDH0R 502 $190 equ canTI1R 503 $194 equ canTDT1R 504 $198 equ canTDL1R 505 $19C equ canTDH1R 506 $1A0 equ canTI2R 507 $1A4 equ canTDT2R 508 $1A8 equ canTDL2R 509 $1AC equ canTDH2R 510 511 $1B0 equ canRI0R 512 $1B4 equ canRDT0R 513 $1B8 equ canRDL0R 514 $1BC equ canRDH0R 515 $1C0 equ canRI1R 516 $1C4 equ canRDT1R 517 $1C8 equ canRDL1R 518 $1CC equ canRDH1R 519 520 $200 equ canFMR 521 $204 equ canFM1R 522 523 $20C equ canFS1R 524 525 $214 equ canFFA1R 526 527 $21C equ canFA1R 528 529 $240 equ canF0R1 $240 equ canFxR1 530 $244 equ canF0R2 $244 equ canFxR2 531 \ ... 532 $318 equ canF27R1 533 $31C equ canF27R2 534 535 536 \ *** 537 \ USB 538 \ *** 539 540 $4000:6000 equ _USBSRAM \ 512 bytes 541 $4000:5C00 equ _USBdev \ device peripheral 542 $00 equ usbEP0R 543 $04 equ usbEP1R 544 $08 equ usbEP2R 545 $0C equ usbEP3R 546 $10 equ usbEP4R 547 $14 equ usbEP5R 548 $18 equ usbEP6R 549 $1C equ usbEP7R 550 551 $40 equ usbCNTR 552 $44 equ usbISTR 553 $48 equ usbFNR 554 $4C equ usbDADDR 555 $50 equ usbBTABLE 556 $54 equ usbLPMCSR 557 $58 equ usbBDCR 558 559 560 \ ******** 561 \ HDMI-CEC 562 \ ******** 563 564 $4000:7800 equ _CEC 565 $00 equ cecCR 566 $04 equ cecCFGR 567 $08 equ cecTXDR 568 $0C equ cecRXDR 569 $10 equ cecISR 570 $14 equ cecIER 571 572 573 \ ************************ 574 \ Exception vector numbers 575 \ ************************ 576 \ Equates of the form xxxVec# refer to Exception Vector position, 577 \ whereas those of the form xxxInt# refer to Interrupt#. 578 \ Nearly all MPE code uses the Vec# form. To convert to Int#, 579 \ subtract 16 from the Vec#. 580 581 #16 equ WWDGvec# 582 #17 equ PVDvec# 583 #18 equ RTCvec# 584 #19 equ FlashVec# 585 #20 equ RCCvec# 586 #21 equ ExtI0_1Vec# 587 #22 equ ExtI2_3Vec# 588 #23 equ ExtI4_15Vec# 589 #24 equ TSCVec# 590 #25 equ DMAC1Vec# 591 #26 equ DMAC2_3Vec# 592 #27 equ DMAC4_5_6_7Vec# 593 #28 equ ADC_COMPvec# 594 #29 equ TIM1_BRK_UP_TRGvec# 595 #30 equ TIM1_CCvec# 596 #31 equ TIM2vec# 597 #32 equ TIM3vec# 598 #33 equ TIM6_DACvec# 599 #34 equ TIM7Vec# 600 #35 equ TIM14vec# 601 #36 equ TIM15vec# 602 #37 equ TIM16vec# 603 #38 equ TIM17vec# 604 #39 equ I2C1_EXTI_23vec# 605 #40 equ I2C2vec# 606 #41 equ SPI1vec# 607 #42 equ SPI2vec# 608 #43 equ USART1_EXTI_25vec# 609 #44 equ USART2_EXTI_26vec# 610 #45 equ USART3_4vec# 611 #46 equ CEC_CAN_EXTI_27vec# 612 #47 equ USB_EXTI_18vec# 613 614 615 \ *********************** 616 \ *S Miscellaneous macros 617 \ *********************** 618 619 interpreter 620 : setMask \ value mask addr -- ; cell operation 621 \ *G Clear the *\i{mask} bits at *\i{addr} and set (or) the 622 \ ** bits defined by *\i{value}. 623 tuck @ \ -- value addr mask x 624 swap invert and \ -- value addr x' 625 rot or \ -- addr x'' 626 swap ! 627 ; 628 target 629 630 631 \ ====== 632 \ *> ### 633 \ ====== 634 635 decimal