startSTM32F072.fth (6655B)
1 \ startSTM32F072.fth - Cortex startup code for SM32F072B-DISCO board 2 3 (( 4 Copyright (c) 2010, 2011, 2012, 2014 5 MicroProcessor Engineering 6 133 Hill Lane 7 Southampton SO15 5AF 8 England 9 10 tel: +44 (0)23 8063 1441 11 fax: +44 (0)23 8033 9691 12 email: mpe@mpeforth.com 13 tech-support@mpeforth.com 14 web: http://www.mpeforth.com 15 Skype: mpe_sfp 16 17 From North America, our telephone and fax numbers are: 18 011 44 23 8063 1441 19 011 44 23 8033 9691 20 901 313 4312 (North American access number to UK office) 21 22 23 To do 24 ===== 25 26 Change history 27 ============== 28 20140205 MPE003 STM32F072 conversion 29 20120322 MPE002 STM32F107 conversion 30 20100112 MPE001 First release. 31 )) 32 33 only forth definitions decimal 34 35 \ =========== 36 \ *! startstm32f072 37 \ *T Cortex start up for STM32F072 38 \ =========== 39 40 l: ExcVecs \ -- addr ; start of vector table 41 \ *G The exception vector table is *\fo{/ExcVecs} bytes long. The 42 \ ** equate is defined in the control file. Note that this table 43 \ ** table must be correctly aligned as described in the Cortex-M3 44 \ ** Technical Reference Manual (ARM DDI0337, rev E page 8-21). If 45 \ ** placed at 0 or the start of Flash, you'll usually be fine. 46 /ExcVecs allot&erase 47 48 interpreter 49 : SetExcVec \ addr exc# -- 50 \ *G Set the given exception vector number to the given address. 51 \ ** Note that for vectors other than 0, the Thumb bit is forced 52 \ ** to 1. 53 dup if \ If not the stack top 54 swap 1 or swap \ set the Thumb bit 55 endif 56 cells ExcVecs + ! ; 57 target 58 59 L: CLD1 \ holds xt of main word 60 0 , \ fixed by MAKE-TURNKEY 61 62 proc DefExc2 b $ end-code \ NMI 63 proc DefExc3 b $ end-code \ HardFault 64 proc DefExc4 b $ end-code \ MemManage 65 proc DefExc5 b $ end-code \ BusFault 66 proc DefExc6 b $ end-code \ UsageFault 67 proc DefExc11 b $ end-code \ SVC 68 proc DefExc12 b $ end-code \ DbgMon 69 proc DefExc14 b $ end-code \ PendSV 70 proc DefExc15 b $ end-code \ SysTick 71 72 73 \ Calculate the initial value for the data stack pointer. 74 \ We allow for TOS being in a register and guard space. 75 76 [undefined] sp-guard [if] \ if no guard value is set 77 0 equ sp-guard 78 [then] 79 80 init-s0 tos-cached? sp-guard + cells - 81 equ real-init-s0 \ -- addr 82 \ The data stack pointer set at start up. 83 84 interpreter 85 : prediv4 \ u -- x 86 \ *G Convert a divider value to a 4 bit pattern as used for HPRE. 87 case 88 1 of %0000 endof 89 2 of %1000 endof 90 4 of %1001 endof 91 8 of %1010 endof 92 16 of %1011 endof 93 64 of %1100 endof 94 128 of %1101 endof 95 256 of %1110 endof 96 512 of %1111 endof 97 true abort" Invalid AHB prescaler setting" 98 endcase 99 ; 100 101 : prediv3 \ u -- x 102 \ *G Convert a divider value to a 3 bit pattern as used for PPRE. 103 case 104 1 of %000 endof 105 2 of %100 endof 106 4 of %101 endof 107 8 of %110 endof 108 16 of %111 endof 109 true abort" Invalid PPREx prescaler setting" 110 endcase 111 ; 112 113 : pllmul1 \ u -- x 114 \ *G Convert a multiplier value to the 4 bit pattern as used for 115 \ ** PLLMUL. 116 dup 2 16 within? 0= abort" Invalid PLLMUL setting" 117 2- 118 ; 119 target 120 121 \ *P We set up for 48 MHz CPU speed from the HSI oscillator. 122 \ ** The HSI oscillator is more accurate than the HSI48, so 123 \ ** the HSI is better for UART use. 124 0 \ also the reset value 125 $04 24 lshift or \ MCO from SystemClock 126 system-speed xtal-speed / pllmul1 127 18 lshift or \ PLLin * x ; PLLin = 8MHz 128 \ bit17 set from bits3:0 in rccCFGR2 129 %01 15 lshift or \ PLLSRC from HSI/PREDIV 130 APBdiv prediv3 8 lshift or \ APB clock 131 AHBdiv prediv4 4 lshift or \ AHB clock 132 equ initCFGRval \ -- x 133 \ *G Bit settings for the RCC_CFGR register. 134 0 135 0 or \ prediv = 0 FOR NO DIVIDE 136 equ initCFGR2val \ -- x 137 \ *G Bit settings for the RCC_CFGR2 register. 138 139 \ *P The number of wait states required by the Flash depends on 140 \ ** the operating frequency. 141 system-speed 1- 24 MHz / equ FLWS \ -- u 142 \ *G The number of Flash wait states required. 143 144 bit4 ( PRFTBE ) FLWS or equ initACRval \ -- x 145 \ *G Initial value written to the FLASH_ACR register 146 147 internal 148 : setClocks \ -- 149 \ *G Enable the clocks, set the bus dividers, and enable the PLLs 150 \ ** as required. the PLL IS used to generate the main 48 MHz 151 \ ** clock. By default, the AHB and APB busses are run at 152 \ ** SYSCLK 153 _RCC 154 155 \ ensure internal clock is running 156 bit0 over rccCR + or! \ set HSION 157 begin 158 dup rccCR + @ bit1 and \ wait for HSIRDY 159 until 160 (( 161 \ start external clock 162 bit16 over rccCR + or! \ set HSEON 163 begin 164 dup rccCR + @ bit17 and \ wait for HSERDY 165 until 166 )) 167 168 \ Set up the Flash configuration 169 initACRval _FPEC flACR + ! \ Enable caches and set wait states 170 171 \ set prescalers and PLL configurations 172 initCFGRval over rccCFGR + ! \ set AHB, APB1, APB2 prescalers 173 initCFGR2val over rccCFGR2 + ! \ PLL2/3 and dividers 174 175 \ start main PLL 176 bit24 over rccCR + or! \ set PLLON 177 begin 178 dup rccCR + @ bit25 and \ wait for PLLRDY 179 until 180 181 \ switch to the PLL output 182 $0002 $0003 2 pick rccCFGR + setMask \ set SW=2 183 begin 184 dup rccCFGR + @ $000C and $0008 = \ wait for SWS=2 185 until 186 187 drop 188 ; 189 190 : StartCortex \ -- ; never exits 191 \ *G Set up the Forth registers and start Forth. Other primary 192 \ ** hardware initialisation can also be performed here. 193 \ ** All the GPIO blocks are enabled. 194 begin 195 INT_STACK_TOP SP_main sys! \ set SP_main for interrupts 196 INIT-R0 SP_process sys! \ set SP_process for tasks 197 2 control sys! \ switch to SP_process 198 REAL-INIT-S0 set-sp \ Allow for cached TOS and guard space 199 INIT-U0 up! \ USER area 200 $007E:0014 _RCC rccAHBen + or! \ enable GPIOs, FLIT and SRAM 201 $007E:0000 _RCC rccAHBrst + bic! \ no reset to GPIOs 202 setClocks 203 CLD1 @ execute 204 again 205 ; 206 external 207 208 INT_STACK_TOP StackVec# SetExcVec \ Define initial return stack 209 ' StartCortex ResetVec# SetExcVec \ Define startup word 210 DefExc2 2 SetExcVec 211 DefExc3 3 SetExcVec 212 DefExc4 4 SetExcVec 213 DefExc5 5 SetExcVec 214 DefExc11 11 SetExcVec 215 DefExc12 12 SetExcVec 216 DefExc14 14 SetExcVec 217 DefExc15 15 SetExcVec 218 219 220 \ ------------------------------------------ 221 \ reset values for user and system variables 222 \ ------------------------------------------ 223 224 [undefined] umbilical? [if] 225 L: USER-RESET 226 init-s0 tos-cached? sp-guard + cells - , \ s0 227 init-r0 , \ r0 228 0 , 0 , \ #tib, 'tib 229 0 , 0 , \ >in, out 230 $0A , 0 , \ base, hld 231 232 \ initial values of system variables 233 L: INIT-FENCE 0 , \ fence 234 L: INIT-DP 0 , \ dp 235 L: INIT-RP 0 , \ RP 236 L: INIT-VOC-LINK 0 , \ voc-link 237 [then] 238 239 240 \ ====== 241 \ *> ### 242 \ ====== 243 244 decimal 245