tab.ctl (11803B)
1 \ liteSTM32F072sa.ctl - STM32F072RB discovery board standalone "Lite" Forth 2 \ Modified for TAB by Duncan Louttit August 2023 onwards 3 4 (( 5 Copyright (c) 2014 6 MicroProcessor Engineering 7 133 Hill Lane 8 Southampton SO15 5AF 9 England 10 11 tel: +44 (0)23 8063 1441 12 fax: +44 (0)23 8033 9691 13 net: mpe@mpeforth.com 14 tech-support@mpeforth.com 15 web: www.mpeforth.com 16 17 From North America, our telephone and fax numbers are: 18 011 44 23 8063 1441 19 011 44 23 8033 9691 20 21 22 To do 23 ===== 24 25 Change history 26 ============== 27 20140205 MPE001 First release for STM32F0xx. 28 )) 29 30 31 \ ================ 32 \ *! stm32f072litesa 33 \ *T Control file for STM32F072 Discovery board 34 \ ================ 35 \ *P The control file tab.ctl 36 \ ** produces a standalone Forth for the STM32F072 Discovery board. 37 \ ** The serial port is connected to USART1 on pins PA9 (Tx) and 38 \ ** PA10 (Rx). 39 \ ** You cannot use the easy GPIO code for UART initialisation unless 40 \ ** the GPIO ports are clocked and taken out of reset in the start 41 \ ** up code. 42 43 \ *P When you modify this file for your own hardware do not forget 44 \ ** to update the GPIO pin assignments and alternate function 45 \ ** selections. 46 47 \ *P You can easily use the low-cost ST-LINK/V2 JTAG unit, or use 48 \ ** the one integrated into the ST Discovery boards. 49 \ ** The ST-LINK Utility software is a 50 \ ** free download from the ST website *\f{www.st.com}. 51 52 only forth definitions decimal 53 54 55 \ ****************************** 56 \ Define the default directories 57 \ ****************************** 58 59 c" ." setmacro AppDir \ application files 60 c" ." setmacro HwDir \ Board hardware files 61 c" ." setmacro CpuDir \ CPU specific files 62 c" ..\Common" setmacro CommonDir \ common high level files 63 c" ..\Examples" setmacro ExampleDir \ example files 64 65 66 \ *************************************** 67 \ Load compiler extensions such as macros 68 \ *************************************** 69 70 include Macros 71 72 73 \ ********************************************************* 74 \ Turn on the cross compiler and define CPU and log options 75 \ ********************************************************* 76 77 \ file: PROG.log \ uncomment to send log to a file 78 79 CROSS-COMPILE 80 81 only forth definitions \ default search order 82 83 no-log \ uncomment to suppress output log 84 rommed \ split ROM/RAM target 85 interactive \ enter interactive mode at end 86 +xrefs \ enable cross references 87 align-long \ code is 32bit aligned 88 Cortex-M0 \ Thumb2 processor type and register usage 89 -LongCalls \ no calls outside 25 bit range 90 +FlashCompile \ target compiles to Flash 91 Hex-I32 \ also produce Intel Hex-32 obj format 92 +SaveCdataOnly \ no data area image files 93 94 0 equ false 95 -1 equ true 96 97 98 \ ******************* 99 \ *S Configure target 100 \ ******************* 101 102 \ ====================== 103 \ *N STM32F0 variant definitions 104 \ ====================== 105 106 $0800:0000 equ FlashBase \ -- addr 107 \ *G Start address of Flash. The bottom 2kb (the vector area) is 108 \ ** mirrored at $0000:0000 for booting. 109 110 #128 kb equ /Flash \ -- len 111 \ *G Size of Flash. 112 2 kb equ /FlashPage \ -- len 113 \ *G Size of a Flash Page. 114 1 equ KeepPages \ -- u 115 \ *G Set this non-zero for the number of pages at the end of Flash 116 \ ** that are reserved for configuration data. Often set to 1 or 2 117 \ ** by systems that use PowerNet. 118 FlashBase /Flash + /FlashPage KeepPages * - equ CfgFlash \ -- len 119 \ *G Base address of the configuration Flash area. 120 121 $1FFF:C800 equ /InfoBase \ -- addr 122 \ *G Base address of system memory information block. 123 124 #12 kb equ /SysMem \ -- len 125 \ *G Size of system memory block. 126 127 $1FFF:F800 equ OptionBytes \ -- addr 128 \ *G Base address of option bytes 129 #16 equ /OptionBytes \ -- len 130 \ *G Number of option bytes 131 132 #64 cells equ /ExcVecs \ -- len 133 \ *G Size of the exception/interrupt vector table. There are 134 \ ** 16 reserved by ARM. 135 136 \ *P The system clocks are generated from PLLs. 137 \ ** How to set them up is non-obvious and is mostly documented 138 \ ** by the ST demonstration code in the file *\i{system_stm32f0x2.c}. 139 \ ** If you are not going to use an existing setup, copy and rename 140 \ ** one of the existing *\i{startSTM32F0xx.fth} files. 141 142 8 MHz equ xtal-speed \ -- hz 143 \ *G Master oscillator crystal clock rate in HZ. This is the HSI 144 \ ** internal oscillator which has better than +/-1% accuracy and 145 \ ** is more accurate than the internal 48 MHz oscillator. 146 48 MHz equ system-speed \ -- hz 147 \ *G Requested CPU clock speed in HZ. Note that you must 148 \ ** calculate the PLL values. 149 150 1 equ AHBdiv \ -- u 151 \ *G Division ratio of the AHB clock from the system clock. 152 \ ** This may not be more than 48 MHz. 153 1 equ APBdiv \ -- u 154 \ *G Division ratio of the APB clock from the system clock. 155 \ ** This may not be more than 48 MHz. 156 157 system-speed AHBdiv / equ AHB-speed \ -- hz 158 \ *G AHB bus speed. 159 system-speed APBdiv / equ APB-speed \ -- hz 160 \ *G APB bus speed. 161 162 163 \ ============= 164 \ *N Memory map 165 \ ============= 166 \ *P If you are using the *\fo{Reflash} code in the *\i{ReProg} 167 \ ** folder, note that the Flash reprogramming code uses RAM 168 \ ** from $2000:0000..$2000:0FFF and its mirrors. Ensure that 169 \ ** your stacks are outside this region. 170 171 \ *P The Flash memory starts at $0800:0000. The bottom 2 kb (the 172 \ ** vector area) is mirrored at $0000:0000. The top 4 kb (two 173 \ ** pages) is used to save autostart and application linkage 174 \ ** information. 175 176 $0800:0000 $0800:BFFF cdata section tab \ code section in boot Flash 177 \ ***** $2000:0000 $2000:0FFF idata section PROGd \ 4k IDATA 178 \ ***** $2000:1000 $2000:3FFF udata section PROGu \ 12k UDATA 179 $2000:0000 $2000:1FFF idata section PROGd \ 8k IDATA 180 $2000:2000 $2000:3FFF udata section PROGu \ 8k UDATA 181 182 interpreter 183 : prog tab ; \ synonym 184 target 185 186 PROG PROGd PROGu CDATA \ use Code for HERE , and so on 187 188 $0801:F000 equ INFOSTART \ 2 pages of 2 kb 189 $0801:F800 equ APPSTART 190 $0801:FFFF equ INFOEND 191 $2000:0000 equ RAMSTART 192 $2000:4000 equ RAMEND 193 $0800:0000 equ FLASHSTART \ start of Main Flash 194 $0810:0000 equ FLASHEND \ end of possible main Flash 195 $0800:C000 equ APPFLASHSTART \ start of application flash 196 $0801:F000 equ APPFLASHEND \ end of application flash 197 $0000:F000 equ /APPFLASH \ size of application flash 198 199 APPFLASHSTART TargetFlashStart \ sets HERE at kernel start up 200 201 \ ============================ 202 \ *N Stack and user area sizes 203 \ ============================ 204 205 $0F0 equ UP-SIZE \ size of each task's user area 206 $0F0 equ SP-SIZE \ size of each task's data stack 207 $0100 equ RP-SIZE \ size of each task's return stack 208 up-size rp-size + sp-size + 209 equ task-size \ size of TASK data area 210 \ define the number of cells of guard space at the top of the data stack 211 #2 equ sp-guard \ can underflow the data stack by this amount 212 213 $0100 equ TIB-LEN \ terminal i/p buffer length 214 215 \ define nesting levels for interrupts and SWIs. 216 2 equ #IRQs \ number of IRQ stacks, 217 \ shared by all IRQs (1 min) 218 0 equ #SVCs \ number of SVC nestings permitted 219 \ 0 is ok if SVCs are unused 220 221 \ ========================== 222 \ *N Serial and ticker rates 223 \ ========================== 224 225 1 equ useUSART1? \ -- n 226 \ *G Set non-zero to compile code for USART1, 227 \ ** device *\fo{Console1}. 228 \ #921600 equ console1-speed 229 #9600 equ console1-speed 230 \ #38400 equ console1-speed 231 \ #115200 equ console1-speed 232 \ *G *\fo{Console1} speed in BPS. 233 234 1 equ useUSART2? \ -- n 235 \ *G Set non-zero to compile code for USART2, 236 \ ** device *\fo{Console2}. 237 #921600 equ console2-speed 238 \ #115200 equ console2-speed 239 \ *G *\fo{Console2} speed in BPS. 240 241 1 equ useUSART3? \ -- n 242 \ *G Set non-zero to compile code for USART3, 243 \ ** device *\fo{Console3}. 244 115200 equ console3-speed 245 \ *G *\fo{Console3} speed in BPS. 246 247 1 equ useUSART4? \ -- n 248 \ *G Set non-zero to compile code for USART4, 249 \ ** device *\fo{Console4}. 250 115200 equ console4-speed 251 \ *G *\fo{Console4} speed in BPS. 252 253 1 equ console-port \ -- n ; Designate serial port for terminal (0..n). 254 \ *G Ports 1..4 are the on-chip UARTs. The internal USB device 255 \ ** is port 10, and bit-banged ports are defined from 20 onwards. 256 257 #1 equ tick-ms \ -- ms 258 \ *G Timebase tick in ms. 259 260 261 \ ===================== 262 \ *N Software selection 263 \ ===================== 264 265 \ Kernel components 266 1 equ ColdChain? \ nz to use cold chain mechanism 267 1 equ tasking? \ true if multitasker needed 268 6 cells equ tcb-size \ for internal consistency check 269 0 equ timebase? \ true for TIMEBASE code 270 1 equ softfp? \ true for software floating point 271 0 equ FullCase? \ true to include ?OF END-CASE NEXTCASE extensions 272 0 equ target-locals? \ true if target local variable sources needed 273 0 equ romforth? \ true for ROMForth handler 274 0 equ blocks? \ true if BLOCK needed 275 $0000 equ sizeofheap \ 0=no heap, nz=size of heap 276 1 equ heap-diags? \ true to include diagnostic code 277 0 equ paged? \ true if ROM or RAM is paged/banked 278 \ 0 equ ENVIRONMENT? \ true if ANS ENVIRONMENT system required 279 280 0 equ PowerNet? \ -- flag 281 \ *G Set non-zero to compile the PowerNet TCP/IP stack. 282 283 284 \ ***************** 285 \ default constants 286 \ ***************** 287 288 cell equ cell \ size of a cell (16 bits) 289 0 equ false 290 -1 equ true 291 292 293 \ ************ 294 \ *S Kernel files 295 \ ************ 296 297 include CM0def \ Cortex generic equates and SFRs 298 include sfrSTM32F072 \ STM32F072 special function registers 299 include StackDef \ Reserve default task and stacks 300 PROGd sec-top 1+ equ UNUSED-TOP PROG \ top of memory for UNUSED 301 include startSTM32F072 \ start up code 302 l: crcslot 303 0 , 304 l: crcstart 305 include CodeM0lite \ low level kernel definitions 306 include FlashSTM32 \ Flash programming code 307 include kernel72lite \ high level kernel definitions 308 include rebootSTM32 \ reboot using watchdog 309 include IntCortex \ interrupt handlers for NVIC 310 include FaultCortex \ fault exception handlers for NVIC 311 312 313 : selio-ser1 \ -- 314 \ *G Example to perform clock and pin selection for USART1 on PA9/10. 315 \ ** You cannot use the easy GPIO code for this unless the GPIO ports 316 \ ** are clocked and taken out of reset in the start up code. 317 \ Clocks and reset 318 _RCC 319 $0000 $0003 2 pick rccCFGR3 + setMask \ PCLK is UART clock 320 bit17 over rccAHBen + or! \ enable clock to GPIOA 321 bit17 over rccAHBrst + bic! \ take it out of reset 322 bit14 over rccAPB2en + or! \ enable clock to USART1 323 bit14 over rccAPB2rst + bic! \ take it out of reset 324 drop 325 \ Default on PA9/10 326 _GPIOA >r 327 $0028:0000 $003C:0000 r@ gpioMODER + setMask \ alternate function on 9/10 328 $0000:0110 $0000:0FF0 r> gpioAFRH + setMask \ AF1 for both 329 ; 330 include gpioSTM32F0xx \ easy pin access 331 include serSTM32F0xxp \ polled serial driver 332 include Dump \ DUMP .S etc development tools 333 334 include SysTickDisco072 335 ' start-clock AtCold 336 337 tasking? [if] 338 include MultiCM0lite \ multitasker 339 [then] 340 341 \ ************* 342 \ *S End of kernel 343 \ ************* 344 345 buildfile tab.no 346 l: version$ 347 build$, 348 l: BuildDate$ 349 DateTime$, 350 351 internal 352 : .banner \ -- 353 cr ." ****************************" 354 ; 355 356 : .CPU \ -- ; display CPU type 357 .banner 358 cr ." MPE PowerForth for STM32F072" 359 CR ." Modified for TAB" 360 cr version$ $. space BuildDate$ $. 361 .banner 362 ; 363 external 364 365 366 \ ******************* 367 \ *S Application code 368 \ ******************* 369 \ ***** 370 CR CR ." so far so good" 371 \ ***** 372 373 include ReFlash \ ReFlash utility 374 include include \ include from AIDE 375 include spiSTM32F0hard \ SPI2 driver 376 377 INCLUDE CURSOR.FTH 378 INCLUDE VT100COLOURS.FTH 379 INCLUDE TABIO.FTH 380 \ INCLUDE YELLOWIO.FTH 381 \ INCLUDE WALLSENSORS.FTH 382 383 progu sec-end cdata constant RP-END \ end of available RAM 384 385 386 \ *************** 387 \ *S Finishing up 388 \ *************** 389 390 libraries \ to resolve common forward references 391 include LibM0M1 392 include LIBRARY 393 end-libs 394 395 decimal 396 397 \ Add a kernel checksum 398 crcstart here crcslot crc32 checksum 399 /DefStart 124 > [if] 400 .( DEFSTART area too big ) abort 401 [then] 402 403 update-build 404 FINIS 405 406 407 \ ====== 408 \ *> ### 409 \ ======