wowio.fth (6609B)
1 \ TAB I/O etc. 2 \ Designed by Duncan Louttit January 2023 3 \ 4 \ 5 \ I/O definitions 6 PA 0 PIO: MOTORENABLE 7 PA 1 PIO: LEFTODO \ left odometry input 8 PA 2 PIO: RF/LRLEDS 9 PA 3 PIO: RHSSENSE \ 10 PA 4 PIO: SPARE1 11 PA 5 PIO: SPARE2 \ 12 PA 6 PIO: SPARE3 13 PA 7 PIO: SPARE4 \ 14 PA 8 PIO: (LPWM) 15 PA 11 PIO: (RPWM) 16 PB 0 PIO: LHSSENSE 17 PB 1 PIO: LF/RRLEDS 18 \ PA 9 console TX CONNG 5 19 \ PA 10 console RX CONNG 4 20 PB 4 PIO: RIGHTODO \ Right odometry input 21 PB 6 pio: LED1 22 PB 8 PIO: INNERLEDS 23 PC 13 PIO: LED2 24 CR ." Pins defined" CR 25 26 \ ****************************** 27 \ Clock enabling for peripherals 28 \ ****************************** 29 30 _RCC rccAHBen + EQU AHBEN 31 _RCC rccAPB2en + EQU APB2EN 32 33 34 : I/OCLOCKS ( --- ) 35 _RCC 36 $0E:0001 OVER rccAHBen + OR! \ Clock to PA,PB,PC,DMA 37 $60A00 OVER rccAPB2en + OR! \ Clock to TIM1,16,17 plus ADC 38 $3 OVER rccAPB1en + OR! \ Clock to TIM2,TIM3 39 $60A00 OVER rccAPB2rst + 2DUP OR! BIC! \ Reset timers 1,15,16 plus ADC 40 $3 OVER rccAPB1rst + 2DUP OR! BIC! \ Reset timers 2 and 3 41 DROP ; 42 43 44 \ ******* Timer use ************ 45 \ T1 generates PWM for the motors 46 \ T2 left odometry 47 \ T3 right odometry 48 \ ***** was T16 sound generation 49 \ T17 fast timebase 50 51 \ ************** 52 \ PWM generation 53 \ ************** 54 \ 10 bit PWM using timer1 channel 1 and channel 4 55 \ PWMA is channel 4 56 \ PWMB is channel 1 57 58 _TIM1 timCCR1 + EQU T1CCR1 59 : PWMR ( n --- . Set PWM1 on period. 1000 max.) 60 T1CCR1 ! ; 61 62 _TIM1 timCCR4 + EQU T1CCR4 63 : PWML ( n --- . Set PWM2 on period. 1000 max.) 64 T1CCR4 ! ; 65 66 468 CONSTANT LEFTSTOP 67 468 CONSTANT RIGHTSTOP 68 : STOPMOTORS ( --- ) 69 LEFTSTOP PWML 70 RIGHTSTOP PWMR ; 71 72 : INITT1 ( --- . Initialise timer1 ) 73 STOPMOTORS 74 _TIM1 75 1000 OVER timARR + ! \ Max PWM value is 1000 76 $60 OVER timCCMR1 + ! \ Ch1 PWM mode 77 $6000 OVER timCCMR2 + ! \ Ch4 PWM mode 78 $1001 OVER timCCER + ! \ Turn output on 79 0 OVER timPSC + ! \ 0 Prescale 80 $8000 OVER timBDTR + ! \ output on 81 1 SWAP ! \ Turn timer on 82 2 (LPWM) ISFUNCTION 83 2 (RPWM) ISFUNCTION ; 84 85 \ *********************** 86 \ Timers 2&3 Odometry period 87 \ *********************** 88 _TIM2 timCCR2 + EQU (LPERIOD) 89 _TIM3 timCCR1 + EQU (RPERIOD) 90 91 : RPERIOD ( --- n ) 92 (LPERIOD) W@ ; 93 94 : LPERIOD ( --- n ) 95 (RPERIOD) W@ ; 96 97 98 : INITPERIOD ( timer --- ) 99 -1 OVER timARR + ! \ 100 47 OVER TIMPSC + ! \ 1MHz clocking. Period in usec. 101 1 OVER TIMCR1 + ! \ Enable timer, counting up 102 $31 SWAP TIMCCER + ! \ CCR1 on rising edge, CCR2 on falling edge 103 ; 104 105 : INITT2/3 ( --- ) 106 _TIM2 $400 OVER timDIER + ! \ DMA on channel 2 of timer 2 107 $164 OVER TIMSMCR + ! \ 1 Filter, rising edge resets, ch2 trigger input 108 $1111 OVER TIMCCMR1 + ! \ 1 filter, select ch2 for both capture inputs 109 INITPERIOD 110 111 _TIM3 $200 OVER timDIER + ! \ DMA on channel 1 of timer 3 112 $154 OVER TIMSMCR + ! \ 1 filter, rising edge resets, ch1 trigger input 113 $1011 OVER TIMCCMR1 + ! \ 1 filter, select ch1 for both capture inputs 114 INITPERIOD 115 116 2 LEFTODO ISFUNCTION 117 1 RIGHTODO ISFUNCTION ; 118 EXTERNAL 119 120 \ ************************ 121 \ DMA based odometry count 122 \ ************************ 123 \ TIM2 channel 2 uses DMA channel 3 124 \ TIM3 channel1 uses DMA channel 4 125 \ Transfer from address $0800:0000 to timer 16 count register. 126 \ Timer 16 is unused so this has no effect. 127 128 _DMA dmaCNDTR3 + EQU (LCOUNT) 129 : RCOUNT ( --- n ) 130 $FFFF (LCOUNT) @ - ; 131 132 : RCOUNTCLEAR ( --- ) 133 _DMA dmaCCR3 + 0 OVER ! 134 $FFFF (LCOUNT) ! \ 65K transfers 135 $31 SWAP ! ; \ Circular, memory to peripheral, enable 136 137 _DMA dmaCNDTR4 + EQU (RCOUNT) 138 : LCOUNT ( --- ) 139 $FFFF (RCOUNT) @ - ; 140 141 : LCOUNTCLEAR ( --- n ) 142 _DMA dmaCCR4 + 0 OVER ! 143 $FFFF (RCOUNT) ! \ 65K transfers 144 $31 SWAP ! ; \ Circular, memory to peripheral, enable 145 146 : DMAINIT3 ( --- ) 147 _DMA 148 _TIM17 timCNT + OVER dmaCPAR3 + ! \ Destination address 149 $0800:0000 SWAP dmaCMAR3 + ! \ Source address 150 LCOUNTCLEAR ; 151 152 : DMAINIT4 ( --- ) 153 _DMA 154 _TIM17 timCNT + OVER dmaCPAR4 + ! \ Destination address 155 $0800:0000 SWAP dmaCMAR4 + ! \ Source address 156 RCOUNTCLEAR ; 157 158 : CLEARCOUNTS ( --- ) 159 LCOUNTCLEAR RCOUNTCLEAR ; 160 161 \ ********* 162 \ ADC setup 163 \ ********* 164 165 \ 1 CONSTANT UNUSED 166 \ 2 CNSTANT UNUSED 167 \ 4 CONSTANT WALL1SEL 168 $8 CONSTANT RFANALOGUE 169 $8 CONSTANT LINE0 \ Right line sensor 170 $10 CONSTANT RWANALOGUE 171 $10 CONSTANT LINE1 \ 3rd left line sensor 172 $20 CONSTANT LFANALOGUE 173 $20 CONSTANT LINE2 \ 2nd left line sensor 174 $40 CONSTANT LWANALOGUE 175 $40 CONSTANT LINE3 \ Left line sensor 176 \ $80 CONSTANT UNUSED 177 \ $100 CONSTANT UNUSED 178 \ $200 CONSTANT UNUSED 179 180 : ANALOGS ( --- . Make analogue inputs. ) 181 \ ***** Needs to be set up 182 ; 183 184 _ADC adcCR + CONSTANT ADC_CR 185 _ADC CONSTANT ADC 186 187 : ADCDONE? ( --- f. ) 188 ADC_CR @ 4 AND 0= ; 189 190 : WAITADCDONE ( --- ) 191 BEGIN ADCDONE? UNTIL ; 192 193 : WAITCALDONE ( --- . Wait till ADC available. ) 194 BEGIN ADC_CR @ 0= UNTIL ; 195 196 : ADCENABLED? ( --- f. ) 197 ADC_CR @ 1 AND ; 198 199 : ADC_CAL ( --- . Calibrate ADC. ) 200 ADCENABLED? IF 2 ADC_CR ! THEN WAITCALDONE 201 0 ADC_CR ! \ Get everything ready 202 $8000:0000 ADC_CR ! \ Start calibration 203 WAITCALDONE ; 204 205 : ADCENABLE ( ---. ) 206 ADC_CAL 1 ADC_CR ! ; 207 208 : WAITREADY ( --- ) 209 BEGIN _ADC @ 1 AND UNTIL ; 210 211 : ADCSTART ( --- ) 212 4 ADC_CR OR! ; 213 214 : INITADC ( --- ) 215 ANALOGS 216 ADC_CAL ADCENABLE WAITREADY 217 _ADC 218 0 OVER adcCFGR1 + ! \ 12 bits, right aligned 219 $8000:0000 OVER adcCFGR2 + ! \ PCLK/4 220 ( 0 ) 4 OVER adcSMPR1 + ! \ 41.5 cycles ( Short ) sampling time 221 DROP ; 222 223 _ADC adcCHSELR + CONSTANT CHSEL \ Channel selection register 224 _ADC adcDR + CONSTANT ADCDATA \ ADC data 225 : (ATOD) ( --- n ) 226 4 ADC_CR OR! \ ADCSTART 227 WAITADCDONE ADCDATA @ ; 228 : ADCCHANNEL ( mask --- ) 229 CHSEL ! ; 230 : ATOD ( mask --- nnn . Bit mask for desired channel ) 231 ADCCHANNEL (ATOD) ; 232 233 \ ******** 234 \ Timer 16 235 \ ******** 236 \ _TIM16 CONSTANT TIMER16 237 \ 238 \ : SOUNDPERIOD ( n ---- . Period in uS. ) 239 \ _TIM16 timARR + ! ; 240 241 \ : SOUNDON ( --- ) 242 \ 1 _TIM16 ! 243 \ 2 SOUND ISFUNCTION ; 244 245 \ : SOUNDOFF ( --- ) 246 \ 0 _TIM16 ! 247 \ SOUND ISOUTPUT 248 \ SOUND CLRPIN ; 249 250 \ : INITT16 ( --- . Initialise timer 16. ) 251 \ _TIM16 252 \ $30 OVER timCCMR1 + ! \ Toggle mode 253 \ 1 OVER timCCER + ! \ Enable output 254 \ $8000 OVER timBDTR + ! \ output on 255 \ 23 SWAP TIMPSC + ! 256 \ SOUNDOFF 257 \ ; 258 259 \ ********************* 260 \ Initialise everything 261 \ ********************* 262 263 : INITSTUFF ( --- ) 264 I/OCLOCKS 265 INITT2/3 266 DMAINIT3 267 DMAINIT4 268 INITT1 269 \ INITT16 270 INITADC ; 271 272 : INITALLI/O ( --- . ) 273 INITSTUFF 274 LF/RRLEDS ISOUTPUT 275 RF/LRLEDS ISOUTPUT 276 RHSSENSE ISANALOG 277 LHSSENSE ISANALOG 278 279 LED1 ISOUTPUT 280 LED2 ISOUTPUT ; 281 282 ' INITALLI/O ATCOLD 283 284