yellowio.fth (7501B)
1 \ Yellow Mouse I/O etc. 2 \ Designed by Duncan Louttit December 2017 3 \ 4 \ There is no CONNA comms connector on Orange Mouse 5 \ CONNB is for line sensors. 6 \ CONNC is left wall sensor 7 \ CONND is left front wall sensor 8 \ CONNE is right front wall sensor 9 \ CONNF is right wall sensor 10 \ CONNG is programming and serial comms 11 \ CONNH is left motor 12 \ CONNI is right motor 13 \ CONNJ is marker sensor connector 14 \ 15 \ I/O definitions 16 PC 13 PIO: RFLED \ Right front wall sensor LED drive 17 PA 1 PIO: LODO \ left odometry input 18 PA 3 PIO: RFSIGNAL \ Also CONNB 6 analogue input 19 PA 4 PIO: RWSIGNAL \ Also CONNB 5 analogue input 20 PA 5 PIO: LFSIGNAL \ Also CONNB 2 analogue input 21 PA 6 PIO: LWSIGNAL \ Also CONNB 1 analogue signal 22 PA 7 PIO: LFLED \ Left front wall sensor LED drive 23 PB 0 PIO: LWLED \ Left wall sensor LED drive 24 PB 1 PIO: SW1 25 PB 2 PIO: SW2 26 PA 8 PIO: (LPWM) 27 \ PA 9 console TX CONNG 5 28 \ PA 10 console RX CONNG 4 29 PA 11 PIO: (RPWM) 30 PA 12 PIO: PWMENABLE 31 PA 14 PIO: LMARKER 32 PA 15 PIO: RMARKER 33 PB 4 PIO: RODO \ Right odometry input 34 PB 5 PIO: GREENLED 35 PB 6 PIO: YELLOWLED 36 PB 7 PIO: REDLED 37 PB 8 PIO: SOUND 38 PB 9 PIO: RWLED 39 CR ." Pins defined" CR 40 41 \ ****************************** 42 \ Clock enabling for peripherals 43 \ ****************************** 44 45 _RCC rccAHBen + EQU AHBEN 46 _RCC rccAPB2en + EQU APB2EN 47 48 49 : I/OCLOCKS ( --- ) 50 _RCC 51 $0E:0001 OVER rccAHBen + OR! \ Clock to PA,PB,PC,DMA 52 $60A00 OVER rccAPB2en + OR! \ Clock to TIM1,16,17 plus ADC 53 $3 OVER rccAPB1en + OR! \ Clock to TIM2,TIM3 54 $60A00 OVER rccAPB2rst + 2DUP OR! BIC! \ Reset timers 1,15,16 plus ADC 55 $3 OVER rccAPB1rst + 2DUP OR! BIC! \ Reset timers 2 and 3 56 DROP ; 57 58 59 \ ******* Timer use ************ 60 \ T1 generates PWM for the motors 61 \ T2 left odometry 62 \ T3 right odometry 63 \ T16 sound generation 64 \ T17 fast timebase 65 66 \ ************** 67 \ PWM generation 68 \ ************** 69 \ 10 bit PWM using timer1 channel 1 and channel 4 70 \ PWMA is channel 4 71 \ PWMB is channel 1 72 73 _TIM1 timCCR1 + EQU T1CCR1 74 : PWML ( n --- . Set PWM1 on period. 1000 max.) 75 T1CCR1 ! ; 76 77 _TIM1 timCCR4 + EQU T1CCR4 78 : PWMR ( n --- . Set PWM2 on period. 1000 max.) 79 T1CCR4 ! ; 80 81 468 CONSTANT LEFTSTOP 82 468 CONSTANT RIGHTSTOP 83 : STOPMOTORS ( --- ) 84 LEFTSTOP PWML 85 RIGHTSTOP PWMR ; 86 87 : INITT1 ( --- . Initialise timer1 ) 88 STOPMOTORS 89 _TIM1 90 1000 OVER timARR + ! \ Max PWM value is 1000 91 $60 OVER timCCMR1 + ! \ Ch1 PWM mode 92 $6000 OVER timCCMR2 + ! \ Ch4 PWM mode 93 $1001 OVER timCCER + ! \ Turn output on 94 0 OVER timPSC + ! \ 0 Prescale 95 $8000 OVER timBDTR + ! \ output on 96 1 SWAP ! \ Turn timer on 97 2 (LPWM) ISFUNCTION 98 2 (RPWM) ISFUNCTION ; 99 100 \ *********************** 101 \ Timers 2&3 Odometry period 102 \ *********************** 103 _TIM2 timCCR2 + EQU (LPERIOD) 104 _TIM3 timCCR1 + EQU (RPERIOD) 105 106 : LPERIOD ( --- n ) 107 (LPERIOD) W@ ; 108 109 : RPERIOD ( --- n ) 110 (RPERIOD) W@ ; 111 112 113 : INITPERIOD ( timer --- ) 114 -1 OVER timARR + ! \ 115 47 OVER TIMPSC + ! \ 1MHz clocking. Period in usec. 116 1 OVER TIMCR1 + ! \ Enable timer, counting up 117 $31 SWAP TIMCCER + ! \ CCR1 on rising edge, CCR2 on falling edge 118 ; 119 120 : INITT2/3 ( --- ) 121 _TIM2 $400 OVER timDIER + ! \ DMA on channel 2 of timer 2 122 $164 OVER TIMSMCR + ! \ 1 Filter, rising edge resets, ch2 trigger input 123 $1111 OVER TIMCCMR1 + ! \ 1 filter, select ch2 for both capture inputs 124 INITPERIOD 125 126 _TIM3 $200 OVER timDIER + ! \ DMA on channel 1 of timer 3 127 $154 OVER TIMSMCR + ! \ 1 filter, rising edge resets, ch1 trigger input 128 $1011 OVER TIMCCMR1 + ! \ 1 filter, select ch1 for both capture inputs 129 INITPERIOD 130 131 2 LODO ISFUNCTION 132 1 RODO ISFUNCTION ; 133 EXTERNAL 134 135 \ ************************ 136 \ DMA based odometry count 137 \ ************************ 138 \ TIM2 channel 2 uses DMA channel 3 139 \ TIM3 channel1 uses DMA channel 4 140 \ Transfer from address $0800:0000 to timer 16 count register. 141 \ Timer 16 is unused so this has no effect. 142 143 _DMA dmaCNDTR3 + EQU (LCOUNT) 144 : LCOUNT ( --- n ) 145 $FFFF (LCOUNT) @ - ; 146 147 : LCOUNTCLEAR ( --- ) 148 _DMA dmaCCR3 + 0 OVER ! 149 $FFFF (LCOUNT) ! \ 65K transfers 150 $31 SWAP ! ; \ Circular, memory to peripheral, enable 151 152 _DMA dmaCNDTR4 + EQU (RCOUNT) 153 : RCOUNT ( --- ) 154 $FFFF (RCOUNT) @ - ; 155 156 : RCOUNTCLEAR ( --- n ) 157 _DMA dmaCCR4 + 0 OVER ! 158 $FFFF (RCOUNT) ! \ 65K transfers 159 $31 SWAP ! ; \ Circular, memory to peripheral, enable 160 161 : DMAINIT3 ( --- ) 162 _DMA 163 _TIM17 timCNT + OVER dmaCPAR3 + ! \ Destination address 164 $0800:0000 SWAP dmaCMAR3 + ! \ Source address 165 LCOUNTCLEAR ; 166 167 : DMAINIT4 ( --- ) 168 _DMA 169 _TIM17 timCNT + OVER dmaCPAR4 + ! \ Destination address 170 $0800:0000 SWAP dmaCMAR4 + ! \ Source address 171 RCOUNTCLEAR ; 172 173 : CLEARCOUNTS ( --- ) 174 LCOUNTCLEAR RCOUNTCLEAR ; 175 176 \ ********* 177 \ ADC setup 178 \ ********* 179 180 \ 1 CONSTANT UNUSED 181 \ 2 CNSTANT UNUSED 182 \ 4 CONSTANT WALL1SEL 183 $8 CONSTANT RFANALOGUE 184 $8 CONSTANT LINE0 \ Right line sensor 185 $10 CONSTANT RWANALOGUE 186 $10 CONSTANT LINE1 \ 3rd left line sensor 187 $20 CONSTANT LFANALOGUE 188 $20 CONSTANT LINE2 \ 2nd left line sensor 189 $40 CONSTANT LWANALOGUE 190 $40 CONSTANT LINE3 \ Left line sensor 191 \ $80 CONSTANT UNUSED 192 \ $100 CONSTANT UNUSED 193 \ $200 CONSTANT UNUSED 194 195 : ANALOGS ( --- . Make analogue inputs. ) 196 RFSIGNAL ISANALOG 197 RWSIGNAL ISANALOG 198 LFSIGNAL ISANALOG 199 LWSIGNAL ISANALOG ; 200 201 _ADC adcCR + CONSTANT ADC_CR 202 _ADC CONSTANT ADC 203 204 : ADCDONE? ( --- f. ) 205 ADC_CR @ 4 AND 0= ; 206 207 : WAITADCDONE ( --- ) 208 BEGIN ADCDONE? UNTIL ; 209 210 : WAITCALDONE ( --- . Wait till ADC available. ) 211 BEGIN ADC_CR @ 0= UNTIL ; 212 213 : ADCENABLED? ( --- f. ) 214 ADC_CR @ 1 AND ; 215 216 : ADC_CAL ( --- . Calibrate ADC. ) 217 ADCENABLED? IF 2 ADC_CR ! THEN WAITCALDONE 218 0 ADC_CR ! \ Get everything ready 219 $8000:0000 ADC_CR ! \ Start calibration 220 WAITCALDONE ; 221 222 : ADCENABLE ( ---. ) 223 ADC_CAL 1 ADC_CR ! ; 224 225 : WAITREADY ( --- ) 226 BEGIN _ADC @ 1 AND UNTIL ; 227 228 : ADCSTART ( --- ) 229 4 ADC_CR OR! ; 230 231 : INITADC ( --- ) 232 ANALOGS 233 ADC_CAL ADCENABLE WAITREADY 234 _ADC 235 0 OVER adcCFGR1 + ! \ 12 bits, right aligned 236 $8000:0000 OVER adcCFGR2 + ! \ PCLK/4 237 ( 0 ) 4 OVER adcSMPR1 + ! \ 41.5 cycles ( Short ) sampling time 238 DROP ; 239 240 _ADC adcCHSELR + CONSTANT CHSEL \ Channel selection register 241 _ADC adcDR + CONSTANT ADCDATA \ ADC data 242 243 : ATOD ( mask --- nnn . Bit mask for desired channel ) 244 CHSEL ! 245 ADCSTART WAITADCDONE 246 ADCDATA @ ; 247 248 \ ******** 249 \ Timer 16 250 \ ******** 251 _TIM16 CONSTANT TIMER16 252 253 : SOUNDPERIOD ( n ---- . Period in uS. ) 254 _TIM16 timARR + ! ; 255 256 : SOUNDON ( --- ) 257 1 _TIM16 ! 258 2 SOUND ISFUNCTION ; 259 260 : SOUNDOFF ( --- ) 261 0 _TIM16 ! 262 SOUND ISOUTPUT 263 SOUND CLRPIN ; 264 265 : INITT16 ( --- . Initialise timer 16. ) 266 _TIM16 267 $30 OVER timCCMR1 + ! \ Toggle mode 268 1 OVER timCCER + ! \ Enable output 269 $8000 OVER timBDTR + ! \ output on 270 23 SWAP TIMPSC + ! 271 SOUNDOFF 272 ; 273 274 \ ********************* 275 \ Initialise everything 276 \ ********************* 277 278 : INITSTUFF ( --- ) 279 I/OCLOCKS 280 INITT2/3 281 DMAINIT3 282 DMAINIT4 283 INITT1 284 INITT16 285 INITADC ; 286 287 : INITALLI/O ( --- . ) 288 INITSTUFF 289 RFLED DUP ISOUTPUT CLRPIN 290 RWLED DUP ISOUTPUT CLRPIN 291 LFLED DUP ISOUTPUT CLRPIN 292 LWLED DUP ISOUTPUT CLRPIN 293 REDLED DUP ISOUTPUT CLRPIN 294 YELLOWLED DUP ISOUTPUT CLRPIN 295 GREENLED DUP ISOUTPUT CLRPIN 296 PWMENABLE DUP ISOUTPUT CLRPIN 297 RMARKER ISINPUT LMARKER ISINPUT 298 SW1 ISINPUT SW2 ISINPUT 299 ; 300 301 ' INITALLI/O ATCOLD 302 303 \ ***************** 304 \ Low level drivers 305 \ ***************** 306 307 : SW1? ( --- f. ) 308 SW1 GETPIN 0= ; 309 310 : SW2? ( --- f. ) 311 SW2 GETPIN 0= ; 312 313 314 315 316 317